1 /* SPDX-License-Identifier: MIT */
2 #ifndef LIBURING_BARRIER_H
3 #define LIBURING_BARRIER_H
4
5 /*
6 From the kernel documentation file refcount-vs-atomic.rst:
7
8 A RELEASE memory ordering guarantees that all prior loads and
9 stores (all po-earlier instructions) on the same CPU are completed
10 before the operation. It also guarantees that all po-earlier
11 stores on the same CPU and all propagated stores from other CPUs
12 must propagate to all other CPUs before the release operation
13 (A-cumulative property). This is implemented using
14 :c:func:`smp_store_release`.
15
16 An ACQUIRE memory ordering guarantees that all post loads and
17 stores (all po-later instructions) on the same CPU are
18 completed after the acquire operation. It also guarantees that all
19 po-later stores on the same CPU must propagate to all other CPUs
20 after the acquire operation executes. This is implemented using
21 :c:func:`smp_acquire__after_ctrl_dep`.
22 */
23
24 #ifdef __cplusplus
25 #include <atomic>
26
27 template <typename T>
IO_URING_WRITE_ONCE(T & var,T val)28 static inline void IO_URING_WRITE_ONCE(T &var, T val)
29 {
30 std::atomic_store_explicit(reinterpret_cast<std::atomic<T> *>(&var),
31 val, std::memory_order_relaxed);
32 }
33 template <typename T>
IO_URING_READ_ONCE(const T & var)34 static inline T IO_URING_READ_ONCE(const T &var)
35 {
36 return std::atomic_load_explicit(
37 reinterpret_cast<const std::atomic<T> *>(&var),
38 std::memory_order_relaxed);
39 }
40
41 template <typename T>
io_uring_smp_store_release(T * p,T v)42 static inline void io_uring_smp_store_release(T *p, T v)
43 {
44 std::atomic_store_explicit(reinterpret_cast<std::atomic<T> *>(p), v,
45 std::memory_order_release);
46 }
47
48 template <typename T>
io_uring_smp_load_acquire(const T * p)49 static inline T io_uring_smp_load_acquire(const T *p)
50 {
51 return std::atomic_load_explicit(
52 reinterpret_cast<const std::atomic<T> *>(p),
53 std::memory_order_acquire);
54 }
55
io_uring_smp_mb()56 static inline void io_uring_smp_mb()
57 {
58 std::atomic_thread_fence(std::memory_order_seq_cst);
59 }
60 #else
61 #include <stdatomic.h>
62
63 #define IO_URING_WRITE_ONCE(var, val) \
64 atomic_store_explicit((_Atomic __typeof__(var) *)&(var), \
65 (val), memory_order_relaxed)
66 #define IO_URING_READ_ONCE(var) \
67 atomic_load_explicit((_Atomic __typeof__(var) *)&(var), \
68 memory_order_relaxed)
69
70 #define io_uring_smp_store_release(p, v) \
71 atomic_store_explicit((_Atomic __typeof__(*(p)) *)(p), (v), \
72 memory_order_release)
73 #define io_uring_smp_load_acquire(p) \
74 atomic_load_explicit((_Atomic __typeof__(*(p)) *)(p), \
75 memory_order_acquire)
76
77 #define io_uring_smp_mb() \
78 atomic_thread_fence(memory_order_seq_cst)
79 #endif
80
81 #endif /* defined(LIBURING_BARRIER_H) */
82