1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <assert.h>
4 #include <device/mmio.h>
5 #include <delay.h>
6 #include <soc/dsi.h>
7 #include <soc/pll.h>
8 #include <types.h>
9
mtk_dsi_configure_mipi_tx(u32 data_rate,u32 lanes)10 void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes)
11 {
12 unsigned int txdiv0, txdiv1;
13 u64 pcw;
14
15 if (data_rate >= 2000 * MHz) {
16 txdiv0 = 0;
17 txdiv1 = 0;
18 } else if (data_rate >= 1000 * MHz) {
19 txdiv0 = 1;
20 txdiv1 = 0;
21 } else if (data_rate >= 500 * MHz) {
22 txdiv0 = 2;
23 txdiv1 = 0;
24 } else if (data_rate > 250 * MHz) {
25 /* (data_rate == 250MHz) is a special case that should go to the
26 else-block below (txdiv0 = 4) */
27 txdiv0 = 3;
28 txdiv1 = 0;
29 } else {
30 /* MIN = 125 */
31 assert(data_rate >= MTK_DSI_DATA_RATE_MIN_MHZ * MHz);
32 txdiv0 = 4;
33 txdiv1 = 0;
34 }
35
36 clrbits32(&mipi_tx->pll_con4, BIT(11) | BIT(10));
37 setbits32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_PWR_ON);
38 udelay(30);
39 clrbits32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_ISO_EN);
40
41 pcw = (u64)data_rate * (1 << txdiv0) * (1 << txdiv1);
42 pcw <<= 24;
43 pcw /= CLK26M_HZ;
44
45 write32(&mipi_tx->pll_con0, pcw);
46 clrsetbits32(&mipi_tx->pll_con1, RG_DSI_PLL_POSDIV, txdiv0 << 8);
47 udelay(30);
48 setbits32(&mipi_tx->pll_con1, RG_DSI_PLL_EN);
49
50 /* BG_LPF_EN / BG_CORE_EN */
51 write32(&mipi_tx->lane_con, 0x3fff0180);
52 udelay(40);
53 write32(&mipi_tx->lane_con, 0x3fff00c0);
54
55 /* Switch OFF each Lane */
56 clrbits32(&mipi_tx->d0_sw_ctl_en, DSI_SW_CTL_EN);
57 clrbits32(&mipi_tx->d1_sw_ctl_en, DSI_SW_CTL_EN);
58 clrbits32(&mipi_tx->d2_sw_ctl_en, DSI_SW_CTL_EN);
59 clrbits32(&mipi_tx->d3_sw_ctl_en, DSI_SW_CTL_EN);
60 clrbits32(&mipi_tx->ck_sw_ctl_en, DSI_SW_CTL_EN);
61
62 setbits32(&mipi_tx->ck_ckmode_en, DSI_CK_CKMODE_EN);
63 }
64
mtk_dsi_reset(void)65 void mtk_dsi_reset(void)
66 {
67 write32(&dsi0->dsi_force_commit,
68 DSI_FORCE_COMMIT_USE_MMSYS | DSI_FORCE_COMMIT_ALWAYS);
69 write32(&dsi0->dsi_con_ctrl, 1);
70 write32(&dsi0->dsi_con_ctrl, 0);
71 }
72