1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <delay.h>
4 #include <device/mmio.h>
5 #include <soc/spm.h>
6
7 enum {
8 SRAM_ISOINT_B = 1U << 6,
9 SRAM_CKISO = 1U << 5,
10 PWR_CLK_DIS = 1U << 4,
11 PWR_ON_2ND = 1U << 3,
12 PWR_ON = 1U << 2,
13 PWR_ISO = 1U << 1,
14 PWR_RST_B = 1U << 0
15 };
16
mtcmos_set_scpd_ext_buck_iso(const struct power_domain_data * pd)17 __weak void mtcmos_set_scpd_ext_buck_iso(const struct power_domain_data *pd)
18 {
19 /* do nothing */
20 }
21
mtcmos_power_on(const struct power_domain_data * pd)22 void mtcmos_power_on(const struct power_domain_data *pd)
23 {
24 write32(&mtk_spm->poweron_config_set,
25 (SPM_PROJECT_CODE << 16) | (1U << 0));
26
27 if (pd->caps & SCPD_EXT_BUCK_ISO)
28 mtcmos_set_scpd_ext_buck_iso(pd);
29
30 setbits32(pd->pwr_con, PWR_ON);
31 setbits32(pd->pwr_con, PWR_ON_2ND);
32
33 while (!(read32(&mtk_spm->pwr_status) & pd->pwr_sta_mask) ||
34 !(read32(&mtk_spm->pwr_status_2nd) & pd->pwr_sta_mask))
35 continue;
36
37 clrbits32(pd->pwr_con, PWR_CLK_DIS);
38 clrbits32(pd->pwr_con, PWR_ISO);
39 setbits32(pd->pwr_con, PWR_RST_B);
40 clrbits32(pd->pwr_con, pd->sram_pdn_mask);
41
42 while (read32(pd->pwr_con) & pd->sram_ack_mask)
43 continue;
44
45 if (pd->caps & SCPD_SRAM_ISO) {
46 setbits32(pd->pwr_con, SRAM_ISOINT_B);
47 udelay(1);
48 clrbits32(pd->pwr_con, SRAM_CKISO);
49 }
50 }
51
mtcmos_display_power_on(void)52 void mtcmos_display_power_on(void)
53 {
54 int i;
55
56 for (i = 0; i < ARRAY_SIZE(disp); i++)
57 mtcmos_power_on(&disp[i]);
58 }
59
mtcmos_audio_power_on(void)60 void mtcmos_audio_power_on(void)
61 {
62 int i;
63
64 for (i = 0; i < ARRAY_SIZE(audio); i++)
65 mtcmos_power_on(&audio[i]);
66 }
67