1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <arch/mmu.h>
4 #include <symbols.h>
5 #include <soc/emi.h>
6 #include <soc/mmu_operations.h>
7
mtk_soc_after_dram(void)8 __weak void mtk_soc_after_dram(void) { /* do nothing */ }
9
mtk_mmu_init(void)10 void mtk_mmu_init(void)
11 {
12 static bool mmu_inited;
13
14 if (mmu_inited)
15 return;
16
17 mmu_inited = true;
18
19 mmu_init();
20
21 /*
22 * Set 0x0 to 8GB address as device memory. We want to config IO_PHYS
23 * address to DEV_MEM, and map a proper range of dram for the memory
24 * test during calibration.
25 */
26 mmu_config_range((void *)0, (uintptr_t)8U * GiB, DEV_MEM);
27
28 /* SRAM is cached */
29 mmu_config_range(_sram, REGION_SIZE(sram), SECURE_CACHED_MEM);
30
31 /* L2C SRAM is cached */
32 mmu_config_range(_sram_l2c, REGION_SIZE(sram_l2c), SECURE_CACHED_MEM);
33
34 /* DMA is non-cached and is reserved for TPM & da9212 I2C DMA */
35 mmu_config_range(_dma_coherent, REGION_SIZE(dma_coherent),
36 SECURE_UNCACHED_MEM);
37
38 mmu_enable();
39 }
40
mtk_mmu_after_dram(void)41 void mtk_mmu_after_dram(void)
42 {
43 /* Map DRAM as cached now that it's up and running */
44 mmu_config_range(_dram, (uintptr_t)sdram_size(), NONSECURE_CACHED_MEM);
45
46 mtk_soc_after_dram();
47 }
48
mtk_mmu_disable_l2c_sram(void)49 void mtk_mmu_disable_l2c_sram(void)
50 {
51 /* Unmap L2C SRAM so it can be reclaimed by L2 cache */
52 /* TODO: Implement true unmapping, and also use it for the zero-page! */
53 mmu_config_range(_sram_l2c, REGION_SIZE(sram_l2c), DEV_MEM);
54
55 /* Careful: changing cache geometry while it's active is a bad idea! */
56 mmu_disable();
57
58 mtk_soc_disable_l2c_sram();
59
60 /* Re-enable MMU with now enlarged L2 cache. Page tables still valid. */
61 mmu_enable();
62 }
63