xref: /aosp_15_r20/external/coreboot/src/soc/mediatek/common/dpm.c (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <device/mmio.h>
4 #include <soc/dpm.h>
5 #include <soc/mcu_common.h>
6 #include <soc/symbols.h>
7 
8 static struct mtk_mcu dpm_mcu[] = {
9 	{
10 		.firmware_name = CONFIG_DPM_DM_FIRMWARE,
11 		.run_address = (void *)DPM_DM_SRAM_BASE,
12 	},
13 	{
14 		.firmware_name = CONFIG_DPM_PM_FIRMWARE,
15 		.run_address = (void *)DPM_PM_SRAM_BASE,
16 		.priv = mtk_dpm,
17 		.reset = dpm_reset,
18 	},
19 };
20 
dpm_reset(struct mtk_mcu * mcu)21 void dpm_reset(struct mtk_mcu *mcu)
22 {
23 	struct dpm_regs *dpm = mcu->priv;
24 
25 	/* write bootargs */
26 	write32(&dpm->twam_window_len, 0x0);
27 	write32(&dpm->twam_mon_type, 0x0);
28 
29 	/* free RST */
30 	setbits32(&dpm->sw_rstn, DPM_SW_RSTN_RESET);
31 }
32 
dpm_init(void)33 int dpm_init(void)
34 {
35 	int i;
36 	struct mtk_mcu *dpm;
37 
38 	if (CONFIG(DPM_FOUR_CHANNEL))
39 		if (dpm_4ch_init())
40 			return -1;
41 
42 	/* config DPM SRAM layout */
43 	clrsetbits32(&mtk_dpm->sw_rstn, DPM_MEM_RATIO_MASK, DPM_MEM_RATIO_CFG1);
44 
45 	for (i = 0; i < ARRAY_SIZE(dpm_mcu); i++) {
46 		dpm = &dpm_mcu[i];
47 		dpm->load_buffer = _dram_dma;
48 		dpm->buffer_size = REGION_SIZE(dram_dma);
49 		if (mtk_init_mcu(dpm))
50 			return -1;
51 	}
52 
53 	if (CONFIG(DPM_FOUR_CHANNEL))
54 		if (dpm_4ch_para_setting())
55 			return -1;
56 
57 	return 0;
58 }
59