Searched +full:xlnx +full:- +full:zynqmp +full:- +full:dpdma (Results 1 – 7 of 7) sorted by relevance
| /linux-6.14.4/Documentation/devicetree/bindings/dma/xilinx/ |
| D | xlnx,zynqmp-dpdma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dpdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP DisplayPort DMA Controller
10 These bindings describe the DMA engine included in the Xilinx ZynqMP
16 - Laurent Pinchart <[email protected]>
19 - $ref: ../dma-controller.yaml#
22 "#dma-cells":
25 The cell is the DMA channel ID (see dt-bindings/dma/xlnx-zynqmp-dpdma.h
[all …]
|
| /linux-6.14.4/Documentation/devicetree/bindings/usb/ |
| D | dwc3-xilinx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mubin Sayyed <[email protected]>
11 - Radhey Shyam Pandey <[email protected]>
16 - enum:
17 - xlnx,zynqmp-dwc3
18 - xlnx,versal-dwc3
22 "#address-cells":
[all …]
|
| /linux-6.14.4/Documentation/gpu/ |
| D | zynqmp.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
4 Xilinx ZynqMP Ultrascale+ DisplayPort Subsystem
7 This subsystem handles DisplayPort video and audio output on the ZynqMP. It
8 supports in-memory framebuffers with the DisplayPort DMA controller
9 (xilinx-dpdma), as well as "live" video and audio from the programmable logic
15 -------
18 though debugfs. The following files in /sys/kernel/debug/dri/X/DP-1/test/
24 active/inactive will re-activate/re-deactivate test mode. When test
34 Enable/disable clock downspreading (spread-spectrum clocking) by
65 symbol-error
[all …]
|
| /linux-6.14.4/Documentation/devicetree/bindings/display/xlnx/ |
| D | xlnx,zynqmp-dpsub.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP DisplayPort Subsystem
10 The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)
14 +------------------------------------------------------------+
15 +--------+ | +----------------+ +-----------+ |
16 | DPDMA | --->| | --> | Video | Video +-------------+ |
17 | 4x vid | | | | | Rendering | -+--> | | | +------+
[all …]
|
| /linux-6.14.4/arch/arm64/boot/dts/xilinx/ |
| D | zynqmp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19 #include <dt-bindings/power/xlnx-zynqmp-power.h>
20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
21 #include <dt-bindings/thermal/thermal.h>
[all …]
|
| /linux-6.14.4/drivers/dma/xilinx/ |
| D | xilinx_dpdma.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx ZynqMP DPDMA Engine driver
5 * Copyright (C) 2015 - 2020 Xilinx, Inc.
28 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
31 #include "../virt-dma.h"
33 /* DPDMA registers */
119 /* DPDMA descriptor fields */
142 * struct xilinx_dpdma_hw_desc - DPDMA hardware descriptor
180 * struct xilinx_dpdma_sw_desc - DPDMA software descriptor
181 * @hw: DPDMA hardware descriptor
[all …]
|
| /linux-6.14.4/ |
| D | MAINTAINERS | 5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-[email protected]
88 F: drivers/scsi/3w-*
[all …]
|