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/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
H A DX86InstrFoldTables.cpp1 //===-- X86InstrFoldTables.cpp - X86 Instruction Folding Tables -----------===//
9 // This file contains the X86 memory folding tables.
31 // because as new instruction are added into holes in the X86 opcode map they
36 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
37 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
38 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
39 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
40 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
41 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
42 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
[all …]
H A DX86InstrInfo.cpp1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
9 // This file contains the X86 implementation of the TargetInstrInfo class.
14 #include "X86.h"
45 #define DEBUG_TYPE "x86-instr-info"
57 " fuse, but the X86 backend currently can't"),
80 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 in X86InstrInfo()
81 : X86::ADJCALLSTACKDOWN32), in X86InstrInfo()
82 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 in X86InstrInfo()
83 : X86::ADJCALLSTACKUP32), in X86InstrInfo()
84 X86::CATCHRET, in X86InstrInfo()
[all …]
H A DX86MCInstLower.cpp1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
9 // This file contains code to lower X86 MachineInstrs to their corresponding
303 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) in SimplifyShortImmForm()
321 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw in SimplifyMOVSX()
322 if (Op0 == X86::AX && Op1 == X86::AL) in SimplifyMOVSX()
323 NewOpcode = X86::CBW; in SimplifyMOVSX()
325 case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl in SimplifyMOVSX()
326 if (Op0 == X86::EAX && Op1 == X86::AX) in SimplifyMOVSX()
327 NewOpcode = X86::CWDE; in SimplifyMOVSX()
329 case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq in SimplifyMOVSX()
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/
H A DX86InstrFoldTables.cpp1 //===-- X86InstrFoldTables.cpp - X86 Instruction Folding Tables -----------===//
9 // This file contains the X86 memory folding tables.
32 // because as new instruction are added into holes in the X86 opcode map they
37 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
38 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
39 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
40 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
41 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
42 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
43 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
[all …]
H A DX86InstrInfo.cpp1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
9 // This file contains the X86 implementation of the TargetInstrInfo class.
14 #include "X86.h"
49 #define DEBUG_TYPE "x86-instr-info"
61 " fuse, but the X86 backend currently can't"),
84 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 in X86InstrInfo()
85 : X86::ADJCALLSTACKDOWN32), in X86InstrInfo()
86 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 in X86InstrInfo()
87 : X86::ADJCALLSTACKUP32), in X86InstrInfo()
88 X86::CATCHRET, in X86InstrInfo()
[all …]
H A DX86MCInstLower.cpp1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
9 // This file contains code to lower X86 MachineInstrs to their corresponding
336 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) in SimplifyShortImmForm()
354 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw in SimplifyMOVSX()
355 if (Op0 == X86::AX && Op1 == X86::AL) in SimplifyMOVSX()
356 NewOpcode = X86::CBW; in SimplifyMOVSX()
358 case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl in SimplifyMOVSX()
359 if (Op0 == X86::EAX && Op1 == X86::AX) in SimplifyMOVSX()
360 NewOpcode = X86::CWDE; in SimplifyMOVSX()
362 case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq in SimplifyMOVSX()
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
H A DX86GenEVEX2VEXTables.inc3 |* X86 EVEX2VEX tables *|
9 // X86 EVEX encoded instructions that have a VEX 128 encoding
13 { X86::VADDPDZ128rm, X86::VADDPDrm },
14 { X86::VADDPDZ128rr, X86::VADDPDrr },
15 { X86::VADDPSZ128rm, X86::VADDPSrm },
16 { X86::VADDPSZ128rr, X86::VADDPSrr },
17 { X86::VADDSDZrm, X86::VADDSDrm },
18 { X86::VADDSDZrm_Int, X86::VADDSDrm_Int },
19 { X86::VADDSDZrr, X86::VADDSDrr },
20 { X86::VADDSDZrr_Int, X86::VADDSDrr_Int },
[all …]
H A DX86GenRegisterInfo.inc18 namespace X86 {
305 } // end namespace X86
309 namespace X86 {
431 } // end namespace X86
436 namespace X86 {
451 } // end namespace X86
1147 { X86::AH },
1148 { X86::AL },
1149 { X86::BH },
1150 { X86::BL },
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/configs/common/lib/Target/X86/
H A DX86GenEVEX2VEXTables.inc3 |* X86 EVEX2VEX tables *|
9 // X86 EVEX encoded instructions that have a VEX 128 encoding
13 { X86::VADDPDZ128rm, X86::VADDPDrm },
14 { X86::VADDPDZ128rr, X86::VADDPDrr },
15 { X86::VADDPSZ128rm, X86::VADDPSrm },
16 { X86::VADDPSZ128rr, X86::VADDPSrr },
17 { X86::VADDSDZrm, X86::VADDSDrm },
18 { X86::VADDSDZrm_Int, X86::VADDSDrm_Int },
19 { X86::VADDSDZrr, X86::VADDSDrr },
20 { X86::VADDSDZrr_Int, X86::VADDSDrr_Int },
[all …]
H A DX86GenCallingConv.inc179 X86::ECX, X86::EDX, X86::R8D, X86::R9D
191 X86::RCX, X86::RDX, X86::R8, X86::R9
203 X86::EDI, X86::ESI, X86::EDX, X86::ECX
215 X86::RDI, X86::RSI, X86::RDX, X86::RCX
237 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
250 X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3
263 X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3
273 if (unsigned Reg = State.AllocateReg(X86::K1)) {
401 if (unsigned Reg = State.AllocateReg(X86::ECX)) {
410 if (unsigned Reg = State.AllocateReg(X86::ECX)) {
[all …]
H A DX86GenRegisterInfo.inc18 namespace X86 {
314 } // end namespace X86
318 namespace X86 {
445 } // end namespace X86
450 namespace X86 {
465 } // end namespace X86
468 namespace X86 {
505 } // end namespace X86
1219 { X86::AH },
1220 { X86::AL },
[all …]
/aosp_15_r20/external/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
15 #include "X86.h"
44 #define DEBUG_TYPE "x86-instr-info"
55 " fuse, but the X86 backend currently can't"),
116 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 in X86InstrInfo()
117 : X86::ADJCALLSTACKDOWN32), in X86InstrInfo()
118 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 in X86InstrInfo()
119 : X86::ADJCALLSTACKUP32), in X86InstrInfo()
120 X86::CATCHRET, in X86InstrInfo()
[all …]
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567/include/llvm/IR/
DIntrinsicsX86.h16 x86_3dnow_pavgusb = 12146, // llvm.x86.3dnow.pavgusb
17 x86_3dnow_pf2id, // llvm.x86.3dnow.pf2id
18 x86_3dnow_pfacc, // llvm.x86.3dnow.pfacc
19 x86_3dnow_pfadd, // llvm.x86.3dnow.pfadd
20 x86_3dnow_pfcmpeq, // llvm.x86.3dnow.pfcmpeq
21 x86_3dnow_pfcmpge, // llvm.x86.3dnow.pfcmpge
22 x86_3dnow_pfcmpgt, // llvm.x86.3dnow.pfcmpgt
23 x86_3dnow_pfmax, // llvm.x86.3dnow.pfmax
24 x86_3dnow_pfmin, // llvm.x86.3dnow.pfmin
25 x86_3dnow_pfmul, // llvm.x86.3dnow.pfmul
[all …]
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r536225/include/llvm/IR/
DIntrinsicsX86.h16 x86_3dnow_pavgusb = 12176, // llvm.x86.3dnow.pavgusb
17 x86_3dnow_pf2id, // llvm.x86.3dnow.pf2id
18 x86_3dnow_pfacc, // llvm.x86.3dnow.pfacc
19 x86_3dnow_pfadd, // llvm.x86.3dnow.pfadd
20 x86_3dnow_pfcmpeq, // llvm.x86.3dnow.pfcmpeq
21 x86_3dnow_pfcmpge, // llvm.x86.3dnow.pfcmpge
22 x86_3dnow_pfcmpgt, // llvm.x86.3dnow.pfcmpgt
23 x86_3dnow_pfmax, // llvm.x86.3dnow.pfmax
24 x86_3dnow_pfmin, // llvm.x86.3dnow.pfmin
25 x86_3dnow_pfmul, // llvm.x86.3dnow.pfmul
[all …]
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r522817/include/llvm/IR/
DIntrinsicsX86.h16 x86_3dnow_pavgusb = 12039, // llvm.x86.3dnow.pavgusb
17 x86_3dnow_pf2id, // llvm.x86.3dnow.pf2id
18 x86_3dnow_pfacc, // llvm.x86.3dnow.pfacc
19 x86_3dnow_pfadd, // llvm.x86.3dnow.pfadd
20 x86_3dnow_pfcmpeq, // llvm.x86.3dnow.pfcmpeq
21 x86_3dnow_pfcmpge, // llvm.x86.3dnow.pfcmpge
22 x86_3dnow_pfcmpgt, // llvm.x86.3dnow.pfcmpgt
23 x86_3dnow_pfmax, // llvm.x86.3dnow.pfmax
24 x86_3dnow_pfmin, // llvm.x86.3dnow.pfmin
25 x86_3dnow_pfmul, // llvm.x86.3dnow.pfmul
[all …]
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567b/include/llvm/IR/
DIntrinsicsX86.h16 x86_3dnow_pavgusb = 12146, // llvm.x86.3dnow.pavgusb
17 x86_3dnow_pf2id, // llvm.x86.3dnow.pf2id
18 x86_3dnow_pfacc, // llvm.x86.3dnow.pfacc
19 x86_3dnow_pfadd, // llvm.x86.3dnow.pfadd
20 x86_3dnow_pfcmpeq, // llvm.x86.3dnow.pfcmpeq
21 x86_3dnow_pfcmpge, // llvm.x86.3dnow.pfcmpge
22 x86_3dnow_pfcmpgt, // llvm.x86.3dnow.pfcmpgt
23 x86_3dnow_pfmax, // llvm.x86.3dnow.pfmax
24 x86_3dnow_pfmin, // llvm.x86.3dnow.pfmin
25 x86_3dnow_pfmul, // llvm.x86.3dnow.pfmul
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/configs/common/include/llvm/IR/
H A DIntrinsicsX86.h16 x86_3dnow_pavgusb = 9907, // llvm.x86.3dnow.pavgusb
17 x86_3dnow_pf2id, // llvm.x86.3dnow.pf2id
18 x86_3dnow_pfacc, // llvm.x86.3dnow.pfacc
19 x86_3dnow_pfadd, // llvm.x86.3dnow.pfadd
20 x86_3dnow_pfcmpeq, // llvm.x86.3dnow.pfcmpeq
21 x86_3dnow_pfcmpge, // llvm.x86.3dnow.pfcmpge
22 x86_3dnow_pfcmpgt, // llvm.x86.3dnow.pfcmpgt
23 x86_3dnow_pfmax, // llvm.x86.3dnow.pfmax
24 x86_3dnow_pfmin, // llvm.x86.3dnow.pfmin
25 x86_3dnow_pfmul, // llvm.x86.3dnow.pfmul
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/
H A DIntrinsicsX86.h16 x86_3dnow_pavgusb = 6322, // llvm.x86.3dnow.pavgusb
17 x86_3dnow_pf2id, // llvm.x86.3dnow.pf2id
18 x86_3dnow_pfacc, // llvm.x86.3dnow.pfacc
19 x86_3dnow_pfadd, // llvm.x86.3dnow.pfadd
20 x86_3dnow_pfcmpeq, // llvm.x86.3dnow.pfcmpeq
21 x86_3dnow_pfcmpge, // llvm.x86.3dnow.pfcmpge
22 x86_3dnow_pfcmpgt, // llvm.x86.3dnow.pfcmpgt
23 x86_3dnow_pfmax, // llvm.x86.3dnow.pfmax
24 x86_3dnow_pfmin, // llvm.x86.3dnow.pfmin
25 x86_3dnow_pfmul, // llvm.x86.3dnow.pfmul
[all …]
/aosp_15_r20/external/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
10 // This file provides X86 specific target descriptions.
70 for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) { in initLLVMToSEHAndCVRegMapping()
77 X86::AL, X86::CL, X86::DL, X86::BL, X86::AH, X86::CH, in initLLVMToSEHAndCVRegMapping()
78 X86::DH, X86::BH, X86::AX, X86::CX, X86::DX, X86::BX, in initLLVMToSEHAndCVRegMapping()
79 X86::SP, X86::BP, X86::SI, X86::DI, X86::EAX, X86::ECX, in initLLVMToSEHAndCVRegMapping()
80 X86::EDX, X86::EBX, X86::ESP, X86::EBP, X86::ESI, X86::EDI, in initLLVMToSEHAndCVRegMapping()
86 MRI->mapLLVMRegToCVReg(X86::EFLAGS, 34); in initLLVMToSEHAndCVRegMapping()
91 MRI->mapLLVMRegToCVReg(X86::FP0 + I, FP0Start + I); in initLLVMToSEHAndCVRegMapping()
96 MRI->mapLLVMRegToCVReg(X86::XMM0 + I, CVXMM0Start + I); in initLLVMToSEHAndCVRegMapping()
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
9 // This file provides X86 specific target descriptions.
74 return MI.getFlags() & X86::IP_HAS_LOCK; in hasLockPrefix()
79 for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) { in initLLVMToSEHAndCVRegMapping()
89 {codeview::RegisterId::AL, X86::AL}, in initLLVMToSEHAndCVRegMapping()
90 {codeview::RegisterId::CL, X86::CL}, in initLLVMToSEHAndCVRegMapping()
91 {codeview::RegisterId::DL, X86::DL}, in initLLVMToSEHAndCVRegMapping()
92 {codeview::RegisterId::BL, X86::BL}, in initLLVMToSEHAndCVRegMapping()
93 {codeview::RegisterId::AH, X86::AH}, in initLLVMToSEHAndCVRegMapping()
94 {codeview::RegisterId::CH, X86::CH}, in initLLVMToSEHAndCVRegMapping()
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
9 // This file provides X86 specific target descriptions.
74 return MI.getFlags() & X86::IP_HAS_LOCK; in hasLockPrefix()
78 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); in isMemOperand()
79 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg); in isMemOperand()
88 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); in is16BitMemOperand()
89 const MCOperand &Index = MI.getOperand(Op + X86::AddrIndexReg); in is16BitMemOperand()
91 if (STI.hasFeature(X86::Is16Bit) && Base.isReg() && Base.getReg() == 0 && in is16BitMemOperand()
94 return isMemOperand(MI, Op, X86::GR16RegClassID); in is16BitMemOperand()
98 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); in is32BitMemOperand()
[all …]
H A DX86InstPrinterCommon.cpp1 //===--- X86InstPrinterCommon.cpp - X86 assembly instruction printing -----===//
32 bool Flavor = MI->getOpcode() == X86::CMPCCXADDmr32 || in printCondCode()
33 MI->getOpcode() == X86::CMPCCXADDmr64; in printCondCode()
114 case X86::VPCOMBmi: case X86::VPCOMBri: OS << "b\t"; break; in printVPCOMMnemonic()
115 case X86::VPCOMDmi: case X86::VPCOMDri: OS << "d\t"; break; in printVPCOMMnemonic()
116 case X86::VPCOMQmi: case X86::VPCOMQri: OS << "q\t"; break; in printVPCOMMnemonic()
117 case X86::VPCOMUBmi: case X86::VPCOMUBri: OS << "ub\t"; break; in printVPCOMMnemonic()
118 case X86::VPCOMUDmi: case X86::VPCOMUDri: OS << "ud\t"; break; in printVPCOMMnemonic()
119 case X86::VPCOMUQmi: case X86::VPCOMUQri: OS << "uq\t"; break; in printVPCOMMnemonic()
120 case X86::VPCOMUWmi: case X86::VPCOMUWri: OS << "uw\t"; break; in printVPCOMMnemonic()
[all …]
/aosp_15_r20/external/clang/test/CodeGen/
H A Dcomplex-math.c1 … %clang_cc1 %s -O1 -emit-llvm -triple x86_64-unknown-unknown -o - | FileCheck %s --check-prefix=X86
2 // RUN: %clang_cc1 %s -O1 -emit-llvm -triple x86_64-pc-win64 -o - | FileCheck %s --check-prefix=X86
3 …N: %clang_cc1 %s -O1 -emit-llvm -triple i686-unknown-unknown -o - | FileCheck %s --check-prefix=X86
9 // X86-LABEL: @add_float_rr( in add_float_rr()
10 // X86: fadd in add_float_rr()
11 // X86-NOT: fadd in add_float_rr()
12 // X86: ret in add_float_rr()
16 // X86-LABEL: @add_float_cr( in add_float_cr()
17 // X86: fadd in add_float_cr()
18 // X86-NOT: fadd in add_float_cr()
[all …]
/aosp_15_r20/out/soong/
Dbootstrap.ninja12 g.bootstrap.ToolDir = out/host/linux-x86/bin
14 g.bootstrap.goRoot = prebuilts/go/linux-x86
80 build out/host/linux-x86/bin/go/aidl-soong-rules/test/android/soong/aidl.a: $
91 out/host/linux-x86/bin/go/blueprint-gobtools/pkg/github.com/google/blueprint/gobtools.a $
92 out/host/linux-x86/bin/go/blueprint-metrics/pkg/github.com/google/blueprint/metrics.a $
93 out/host/linux-x86/bin/go/blueprint-parser/pkg/github.com/google/blueprint/parser.a $
94 out/host/linux-x86/bin/go/blueprint-deptools/pkg/github.com/google/blueprint/deptools.a $
95 out/host/linux-x86/bin/go/blueprint-pathtools/pkg/github.com/google/blueprint/pathtools.a $
96 out/host/linux-x86/bin/go/blueprint-optional/pkg/github.com/google/blueprint/optional.a $
97 out/host/linux-x86/bi
[all...]
/aosp_15_r20/out/soong/.intermediates/system/core/libcutils/libcutils/linux_glibc_x86_64_static/obj/system/core/libcutils/
Dproperties.o.d4 …prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.17-4.8/sysroot/usr/include/x86_64-linux-gnu/sys/c…
5 prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.17-4.8/sysroot/usr/include/features.h \
6 prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.17-4.8/sysroot/usr/include/stdc-predef.h \
7 …prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.17-4.8/sysroot/usr/include/x86_64-linux-gnu/bits/…
8 …prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.17-4.8/sysroot/usr/include/x86_64-linux-gnu/gnu/s…
9 …prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.17-4.8/sysroot/usr/include/x86_64-linux-gnu/gnu/s…
10 …prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.17-4.8/sysroot/usr/include/x86_64-linux-gnu/bits/…
11 prebuilts/clang/host/linux-x86/clang-r536225/include/c++/v1/stddef.h \
12 prebuilts/clang/host/linux-x86/clang-r536225/include/c++/v1/__config \
13 …prebuilts/clang/host/linux-x86/clang-r536225/include/x86_64-unknown-linux-gnu/c++/v1/__config_site…
[all …]

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