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/linux-6.14.4/Documentation/devicetree/bindings/memory-controllers/
Dti,gpmc-child.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <[email protected]>
11 - Roger Quadros <[email protected]>
24 gpmc,sync-clk-ps:
28 # Chip-select signal timings corresponding to GPMC_CONFIG2:
29 gpmc,cs-on-ns:
33 gpmc,cs-rd-off-ns:
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/linux-6.14.4/drivers/mmc/host/
Dsdhci-of-dwcmshc.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/arm-smccc.h>
14 #include <linux/dma-mapping.h>
24 #include "sdhci-pltfm.h"
41 /* Tuning and auto-tuning fields in AT_CTRL_R control register */
51 #define AT_CTRL_PRE_CHANGE_DLY 0x1 /* 2-cycle latency */
53 #define AT_CTRL_POST_CHANGE_DLY 0x3 /* 4-cycle latency */
151 #define PHY_PAD_TXSLEW_CTRL_P 0x3 /* Slew control for P-Type pad TX */
153 #define PHY_PAD_TXSLEW_CTRL_N 0x3 /* Slew control for N-Type pad TX */
154 #define PHY_PAD_TXSLEW_CTRL_N_SG2042 0x2 /* Slew control for N-Type pad TX for SG2042 */
[all …]
Dsdhci-of-sparx5.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/mmc/host/sdhci-of-sparx5.c
13 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
20 #include "sdhci-pltfm.h"
46 ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))
49 * If DMA addr spans 128MB boundary, we split the DMA transfer into two
64 mmc_hostname(host->mmc), len, &addr); in sdhci_sparx5_adma_write_desc()
66 offset = addr & (SZ_128M - 1); in sdhci_sparx5_adma_write_desc()
67 tmplen = SZ_128M - offset; in sdhci_sparx5_adma_write_desc()
[all …]
Ddw_mmc-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/mmc/slot-gpio.h>
16 #include "dw_mmc-pltfm.h"
41 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
46 unsigned long rate = clk_get_rate(host->ciu_clk); in rockchip_mmc_get_internal_phase()
78 struct dw_mci_rockchip_priv_data *priv = host->priv; in rockchip_mmc_get_phase()
79 struct clk *clock = sample ? priv->sample_clk : priv->drv_clk; in rockchip_mmc_get_phase()
81 if (priv->internal_phase) in rockchip_mmc_get_phase()
89 unsigned long rate = clk_get_rate(host->ciu_clk); in rockchip_mmc_set_internal_phase()
93 u32 delay; in rockchip_mmc_set_internal_phase() local
[all …]
Dsdhci-of-ma35d1.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Author: Shan-Chun Hung <[email protected]>
13 #include <linux/delay.h>
16 #include <linux/dma-mapping.h>
32 #include "sdhci-pltfm.h"
69 * If DMA addr spans 128MB boundary, we split the DMA transfer into two
77 if (likely(!len || (ALIGN(addr, SZ_128M) == ALIGN(addr + len - 1, SZ_128M)))) { in ma35_adma_write_desc()
82 offset = addr & (SZ_128M - 1); in ma35_adma_write_desc()
83 tmplen = SZ_128M - offset; in ma35_adma_write_desc()
87 len -= tmplen; in ma35_adma_write_desc()
[all …]
/linux-6.14.4/tools/testing/selftests/net/mptcp/
Dmptcp_connect.sh2 # SPDX-License-Identifier: GPL-2.0
5 # code but we accept it, especially because there were too many before having
36 port=$((10000 - 1))
38 if [ $tc_loss -eq 100 ];then
40 elif [ $tc_loss -ge 10 ]; then
42 elif [ $tc_loss -ge 1 ]; then
49 echo "Usage: $0 [ -a ]"
50 echo -e "\t-d: tc/netem delay in milliseconds, e.g. \"-d 10\" (default random)"
51 echo -e "\t-l: tc/netem loss percentage, e.g. \"-l 0.02\" (default random)"
52 …echo -e "\t-r: tc/netem reorder mode, e.g. \"-r 25% 50% gap 5\", use "-r 0" to disable reordering …
[all …]
/linux-6.14.4/drivers/input/keyboard/
Datkbd.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 1999-2002 Vojtech Pavlik
12 * input-only controllers and AT keyboards connected over a one way RS232
16 #include <linux/delay.h>
22 #include <linux/input/vivaldi-fmap.h>
58 MODULE_PARM_DESC(scroll, "Enable scroll-wheel on MS Office and similar keyboards");
61 module_param_named(extra, atkbd_extra, bool, 0);
62 MODULE_PARM_DESC(extra, "Enable extra LEDs and keys on IBM RapidAcces, EzKey and similar keyboards"…
216 bool extra; member
236 /* Serializes reconnect(), attr->set() and event work */
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/linux-6.14.4/drivers/gpu/drm/i915/
DKconfig.profile19 When listening to a foreign fence, we install a supplementary timer
20 to ensure that we are always signaled and our userspace is able to
28 int "Runtime autosuspend delay for userspace GGTT mmaps (ms)"
31 On runtime suspend, as we suspend the device, we have to revoke
34 the GGTT mmap can be very slow and so we impose a small hysteris
35 that complements the runtime-pm autosuspend and provides a lower
36 floor on the autosuspend delay.
38 May be 0 to disable the extra delay and solely use the device level
39 runtime pm autosuspend delay tunable.
46 check the health of the GPU and undertake regular house-keeping of
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/linux-6.14.4/drivers/clk/rockchip/
Dclk-mmc-phase.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
40 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
57 raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift); in rockchip_mmc_get_phase()
81 u32 delay; in rockchip_mmc_set_phase() local
92 * most likely problem we often face and which makes it difficult in rockchip_mmc_set_phase()
97 return -EINVAL; in rockchip_mmc_set_phase()
104 * Due to the inexact nature of the "fine" delay, we might in rockchip_mmc_set_phase()
105 * actually go non-monotonic. We don't go _too_ monotonic in rockchip_mmc_set_phase()
106 * though, so we should be OK. Here are options of how we may in rockchip_mmc_set_phase()
[all …]
/linux-6.14.4/drivers/input/mouse/
Dsermouse.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 1999-2001 Vojtech Pavlik
10 #include <linux/delay.h>
44 struct input_dev *dev = sermouse->dev; in sermouse_process_msc()
45 signed char *buf = sermouse->buf; in sermouse_process_msc()
47 switch (sermouse->count) { in sermouse_process_msc()
60 input_report_rel(dev, REL_Y, -buf[1]); in sermouse_process_msc()
61 buf[0] = data - data / 2; in sermouse_process_msc()
67 input_report_rel(dev, REL_Y, buf[1] - data); in sermouse_process_msc()
74 if (++sermouse->count == 5) in sermouse_process_msc()
[all …]
/linux-6.14.4/arch/um/drivers/
Dvirt-pci.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/virtio-uml.h>
15 #include <linux/delay.h>
24 /* for MSI-X we have a 32-bit payload */
76 if (!test_and_set_bit(i, dev->used_bufs)) in um_pci_get_buf()
88 if (buf == &dev->bufs[UM_PCI_WRITE_BUFS]) { in um_pci_free_buf()
89 kfree(dev->extra_ptrs[UM_PCI_WRITE_BUFS]); in um_pci_free_buf()
90 dev->extra_ptrs[UM_PCI_WRITE_BUFS] = NULL; in um_pci_free_buf()
95 if (buf == &dev->bufs[i]) { in um_pci_free_buf()
96 kfree(dev->extra_ptrs[i]); in um_pci_free_buf()
[all …]
/linux-6.14.4/drivers/parport/
Ddaisy.c11 * ??-12-1998: Initial implementation.
12 * 31-01-1999: Make port-cloning transparent.
13 * 13-02-1999: Move DeviceID technique from parport_probe.
14 * 13-03-1999: Get DeviceID from non-IEEE 1284.3 devices too.
15 * 22-02-2000: Count devices that are actually detected.
24 #include <linux/delay.h>
44 /* Forward-declaration of lower-level functions. */
56 newdev->port = port; in add_dev()
57 newdev->daisy = daisy; in add_dev()
58 newdev->devnum = devnum; in add_dev()
[all …]
/linux-6.14.4/include/linux/platform_data/
Dgpmc-omap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
34 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
47 /* WE signals timings corresponding to GPMC_CONFIG4 */
48 u32 we_on; /* WE assertion time */
49 u32 we_off; /* WE deassertion time */
58 u32 page_burst_access; /* Multiple access word delay */
59 u32 access; /* Start-cycle to first data valid delay */
99 u32 t_weasu; /* address setup to WE valid */
105 u32 t_bacc; /* burst access valid clock to output delay */
[all …]
/linux-6.14.4/drivers/iio/adc/
Dad4695.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include <linux/delay.h>
33 #include <dt-bindings/iio/adc/adi,ad4695.h>
139 * to control CS and add a delay between the last SCLK and next
189 .name = "ad4695-8",
219 .name = "ad4695-16",
296 * ad4695_set_single_cycle_mode - Set the device in single cycle mode
300 * As per the datasheet, to enable single cycle mode, we need to set
312 ret = regmap_clear_bits(st->regmap, AD4695_REG_SEQ_CTRL, in ad4695_set_single_cycle_mode()
318 ret = regmap_write(st->regmap, AD4695_REG_AS_SLOT(0), in ad4695_set_single_cycle_mode()
[all …]
/linux-6.14.4/fs/ocfs2/dlm/
Ddlmthread.c1 // SPDX-License-Identifier: GPL-2.0-or-later
23 #include <linux/delay.h>
40 /* will exit holding res->spinlock, but may drop in function */
41 /* waits until flags are cleared on res->state */
46 assert_spin_locked(&res->spinlock); in __dlm_wait_on_lockres_flags()
48 add_wait_queue(&res->wq, &wait); in __dlm_wait_on_lockres_flags()
51 if (res->state & flags) { in __dlm_wait_on_lockres_flags()
52 spin_unlock(&res->spinlock); in __dlm_wait_on_lockres_flags()
54 spin_lock(&res->spinlock); in __dlm_wait_on_lockres_flags()
57 remove_wait_queue(&res->wq, &wait); in __dlm_wait_on_lockres_flags()
[all …]
/linux-6.14.4/drivers/phy/intel/
Dphy-intel-keembay-emmc.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/delay.h>
66 ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, PWR_DOWN_MASK, in keembay_emmc_phy_power()
69 dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret); in keembay_emmc_phy_power()
73 ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, DLL_EN_MASK, in keembay_emmc_phy_power()
76 dev_err(&phy->dev, "turn off the dll failed: %d\n", ret); in keembay_emmc_phy_power()
84 mhz = DIV_ROUND_CLOSEST(clk_get_rate(priv->emmcclk), 1000000); in keembay_emmc_phy_power()
100 dev_warn(&phy->dev, "Unsupported rate: %d MHz\n", mhz); in keembay_emmc_phy_power()
105 * value, so we may need a little margin here in keembay_emmc_phy_power()
109 ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, PWR_DOWN_MASK, in keembay_emmc_phy_power()
[all …]
Dphy-intel-lgm-emmc.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/delay.h>
64 ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, PDB_MASK, in intel_emmc_phy_power()
67 dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret); in intel_emmc_phy_power()
75 rate = clk_get_rate(priv->emmcclk); in intel_emmc_phy_power()
78 dev_warn(&phy->dev, "Unsupported rate: %lu\n", rate); in intel_emmc_phy_power()
84 * value, so we may need a little margin here in intel_emmc_phy_power()
88 ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, PDB_MASK, in intel_emmc_phy_power()
91 dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret); in intel_emmc_phy_power()
99 * failure cases are found which indicates we should be more tolerant in intel_emmc_phy_power()
[all …]
/linux-6.14.4/arch/arm64/boot/dts/qcom/
Dsc7180-trogdor-parade-ps8640.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
11 pp3300_brij_ps8640: pp3300-brij-ps8640-regulator {
12 compatible = "regulator-fixed";
14 regulator-name = "pp3300_brij_ps8640";
16 regulator-min-microvolt = <3300000>;
17 regulator-max-microvolt = <3300000>;
20 enable-active-high;
22 pinctrl-names = "default";
23 pinctrl-0 = <&en_pp3300_edp_brij_ps8640>;
[all …]
Dsc7180-trogdor-ti-sn65dsi86.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
17 off-on-delay-us = <500000>;
22 * extra power cycle of the touchscreen and eDP panel at bootup.
23 * This should help speed bootup because we have off-on-delay-us.
25 regulator-boot-on;
32 clock-frequency = <400000>;
37 pinctrl-names = "default";
38 pinctrl-0 = <&edp_brij_en>, <&edp_brij_irq>;
39 gpio-controller;
[all …]
/linux-6.14.4/net/ipv4/
Dtcp_vegas.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * IEEE Journal on Selected Areas in Communication, 13(8):1465--1480,
15 * o We do not change the loss detection or recovery mechanisms of
17 * using fine-grained timers, NewReno, and FACK.
19 * only every-other RTT during slow start, we increase during
22 * we use the rate at which ACKs come back as the "actual"
24 * o To speed convergence to the right rate, we set the cwnd
25 * to achieve the right ("actual") rate when we exit slow start.
26 * o To filter out the noise caused by delayed ACKs, we use the
29 * o When the sender re-starts from idle, it waits until it has
[all …]
/linux-6.14.4/arch/sparc/kernel/
Dsmp_32.c1 // SPDX-License-Identifier: GPL-2.0
23 #include <linux/delay.h>
65 "clock-frequency", 0); in smp_store_cpu_info()
130 sparc32_ipi_ops->resched(cpu); in arch_smp_send_reschedule()
140 sparc32_ipi_ops->single(cpu); in arch_send_call_function_single_ipi()
149 sparc32_ipi_ops->mask_one(cpu); in arch_send_call_function_ipi_mask()
158 /* re-schedule routine called by interrupt return code. */ in smp_resched_interrupt()
179 int i, cpuid, extra; in smp_prepare_cpus() local
183 extra = 0; in smp_prepare_cpus()
186 extra++; in smp_prepare_cpus()
[all …]
/linux-6.14.4/drivers/reset/
Dreset-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/delay.h>
14 #include <linux/reset-controller.h>
29 /* A full bank contains extra registers that we are not utilizing but still
46 writel_relaxed(SW_INIT_BIT(id), priv->base + off + SW_INIT_SET); in brcmstb_reset_assert()
57 writel_relaxed(SW_INIT_BIT(id), priv->base + off + SW_INIT_CLEAR); in brcmstb_reset_deassert()
58 /* Maximum reset delay after de-asserting a line and seeing block in brcmstb_reset_deassert()
73 return readl_relaxed(priv->base + off + SW_INIT_STATUS) & in brcmstb_reset_status()
85 struct device *kdev = &pdev->dev; in brcmstb_reset_probe()
91 return -ENOMEM; in brcmstb_reset_probe()
[all …]
/linux-6.14.4/include/uapi/linux/media/raspberrypi/
Dpisp_fe_config.h1 /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
5 * Copyright (C) 2021 - Raspberry Pi Ltd.
48 * We use the enable flags to show when blocks are "dirty", but we need some
49 * extra ones too.
90 /* Extra cycles delay before issuing each burst request */
268 /* non-register fields: */
/linux-6.14.4/include/linux/usb/
Dquirks.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 /* string descriptors must not be fetched using a 255-byte read */
17 /* device can't handle Set-Interface requests */
30 /* device needs a pause during initialization, after we read the device
38 * interval = 2 ^ (bInterval-1).
69 /* Hub needs extra delay after resetting its port. */
/linux-6.14.4/drivers/fpga/
Dxilinx-core.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include "xilinx-core.h"
12 #include <linux/delay.h>
13 #include <linux/fpga/fpga-mgr.h>
19 struct xilinx_fpga_core *core = mgr->priv; in get_done_gpio()
22 ret = gpiod_get_value(core->done); in get_done_gpio()
24 dev_err(&mgr->dev, "Error reading DONE (%d)\n", ret); in get_done_gpio()
38 * wait_for_init_b - wait for the INIT_B pin to have a given state, or wait
39 * a given delay if the pin is unavailable
43 * @alt_udelay: Delay to wait if the INIT_B GPIO is not available
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