Searched +full:wdt +full:- +full:r1p2 (Results 1 – 4 of 4) sorted by relevance
| /linux-6.14.4/Documentation/devicetree/bindings/watchdog/ |
| D | cdns,wdt-r1p2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/cdns,wdt-r1p2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neeli Srinivas <[email protected]>
19 - $ref: watchdog.yaml#
24 - cdns,wdt-r1p2
35 reset-on-timeout:
42 - compatible
43 - reg
[all …]
|
| /linux-6.14.4/drivers/watchdog/ |
| D | cadence_wdt.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Cadence WDT driver - Used by Xilinx Zynq
5 * Copyright (C) 2010 - 2014 Xilinx, Inc.
21 /* Supports 1 - 516 sec */
63 * struct cdns_wdt - Watchdog device structure
85 static inline void cdns_wdt_writereg(struct cdns_wdt *wdt, u32 offset, u32 val) in cdns_wdt_writereg() argument
87 writel_relaxed(val, wdt->regs + offset); in cdns_wdt_writereg()
92 /* Register Offsets for the WDT */
99 * Zero Mode Register - This register controls how the time out is indicated
102 #define CDNS_WDT_ZMR_WDEN_MASK 0x00000001 /* Enable the WDT */
[all …]
|
| /linux-6.14.4/arch/arm/boot/dts/xilinx/ |
| D | zynq-7000.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "xlnx,zynq-7000";
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,cortex-a9";
20 clock-latency = <1000>;
21 cpu0-supply = <®ulator_vccpint>;
[all …]
|
| /linux-6.14.4/arch/arm64/boot/dts/xilinx/ |
| D | zynqmp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19 #include <dt-bindings/power/xlnx-zynqmp-power.h>
20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
21 #include <dt-bindings/thermal/thermal.h>
25 #address-cells = <2>;
[all …]
|