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/aosp_15_r20/external/cronet/third_party/cpu_features/src/src/
H A Dimpl_x86__base_implementation.inl862 .ways = 4,
870 .ways = 0xFF,
878 .ways = 4,
886 .ways = 4,
894 .ways = 4,
902 .ways = 4,
910 .ways = 4,
918 .ways = 4,
926 .ways = 2,
934 .ways = 4,
[all …]
/aosp_15_r20/external/cpu_features/src/
H A Dimpl_x86__base_implementation.inl873 .ways = 4,
881 .ways = 0xFF,
889 .ways = 4,
897 .ways = 4,
905 .ways = 4,
913 .ways = 4,
921 .ways = 4,
929 .ways = 4,
937 .ways = 2,
945 .ways = 4,
[all …]
/aosp_15_r20/external/lzma/Asm/x86/
H A DAesOpt.asm105 ways = 11 define
107 ways = 4 define
112 iv equ @CatStr(xmm, %(ways_start_reg + ways))
113 iv_ymm equ @CatStr(ymm, %(ways_start_reg + ways))
118 rept ways
256 key0 equ @CatStr(xmm, %(ways_start_reg + ways + 1))
257 key0_ymm equ @CatStr(ymm, %(ways_start_reg + ways + 1))
259 key_last equ @CatStr(xmm, %(ways_start_reg + ways + 2))
260 key_last_ymm equ @CatStr(ymm, %(ways_start_reg + ways + 2))
261 key_last_ymm_n equ (ways_start_reg + ways + 2)
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/aosp_15_r20/external/eigen/Eigen/src/Core/util/
H A DMemory.h972 int ways = (abcd[1] & 0xFFC00000) >> 22; // B[31:22]
977 int cache_size = (ways+1) * (partitions+1) * (line_size+1) * (sets+1);
1003 case 0x0A: l1 = 8; break; // 0Ah data L1 cache, 8 KB, 2 ways, 32 byte lines
1004 case 0x0C: l1 = 16; break; // 0Ch data L1 cache, 16 KB, 4 ways, 32 byte lines
1005 case 0x0E: l1 = 24; break; // 0Eh data L1 cache, 24 KB, 6 ways, 64 byte lines
1006 case 0x10: l1 = 16; break; // 10h data L1 cache, 16 KB, 4 ways, 32 byte lines (IA-64)
1007 case 0x15: l1 = 16; break; // 15h code L1 cache, 16 KB, 4 ways, 32 byte lines (IA-64)
1008 case 0x2C: l1 = 32; break; // 2Ch data L1 cache, 32 KB, 8 ways, 64 byte lines
1009 case 0x30: l1 = 32; break; // 30h code L1 cache, 32 KB, 8 ways, 64 byte lines
1010 case 0x60: l1 = 16; break; // 60h data L1 cache, 16 KB, 8 ways, 64 byte lines, sectored
[all …]
/aosp_15_r20/external/coreboot/src/vendorcode/cavium/bdk/libbdk-hal/
H A Dbdk-l2c.c50 int ways; member
101 l2_node_state[node].ways = ccsidr_el1.s.associativity + 1; in bdk_l2c_get_num_sets()
103 /* Early chips didn't update the number of ways based on fusing */ in bdk_l2c_get_num_sets()
104 if ((l2_node_state[node].ways == 16) && CAVIUM_IS_MODEL(CAVIUM_CN8XXX)) in bdk_l2c_get_num_sets()
111 l2_node_state[node].ways *= 1; in bdk_l2c_get_num_sets()
114 l2_node_state[node].ways *= 2; in bdk_l2c_get_num_sets()
117 l2_node_state[node].ways *= 3; in bdk_l2c_get_num_sets()
120 l2_node_state[node].ways *= 4; in bdk_l2c_get_num_sets()
123 l2_node_state[node].ways /= 4; in bdk_l2c_get_num_sets()
132 /* Get the number of sets if the global sets/ways is not setup */ in bdk_l2c_get_num_assoc()
[all …]
/aosp_15_r20/external/coreboot/src/vendorcode/cavium/include/bdk/libbdk-hal/
H A Dbdk-l2c.h73 * the cache 'ways' that a core can evict from.
84 * @param mask The partitioning of the ways expressed as a binary mask. A 0 bit allows the core
88 * @note If any ways are blocked for all cores and the HW blocks, then those ways will never have
90 * all ways regardless of the partitioning.
99 * the cache 'ways' that a core can evict from.
109 * @param mask The partitioning of the ways expressed as a binary mask. A 0 bit allows the core
113 * @note If any ways are blocked for all cores and the HW blocks, then those ways will never have
115 * all ways regardless of the partitioning.
123 * but one of the ways (associations) available to the locking
/aosp_15_r20/external/coreboot/src/vendorcode/cavium/bdk/libdram/
H A Ddram-l2c.c46 int limit_l2_ways(bdk_node_t node, int ways, int verbose) in limit_l2_ways() argument
52 if (ways >= ways_min && ways <= ways_max) in limit_l2_ways()
55 uint32_t mask = (valid_mask << ways) & valid_mask; in limit_l2_ways()
57 printf("Limiting L2 to %d ways\n", ways); in limit_l2_ways()
66 ways, ways_min, ways_max); in limit_l2_ways()
69 puts("ERROR limiting L2 cache ways\n"); in limit_l2_ways()
/aosp_15_r20/external/cronet/third_party/cpu_features/src/test/
H A Dcpuinfo_x86_test.cc284 EXPECT_EQ(info.levels[0].ways, 8); in TEST_F()
293 EXPECT_EQ(info.levels[1].ways, 8); in TEST_F()
301 EXPECT_EQ(info.levels[2].ways, 4); in TEST_F()
309 EXPECT_EQ(info.levels[3].ways, 12); in TEST_F()
334 EXPECT_EQ(info.levels[0].ways, 8); in TEST_F()
343 EXPECT_EQ(info.levels[1].ways, 8); in TEST_F()
351 EXPECT_EQ(info.levels[2].ways, 8); in TEST_F()
359 EXPECT_EQ(info.levels[3].ways, 12); in TEST_F()
519 EXPECT_EQ(info.levels[0].ways, 4); in TEST_F()
528 EXPECT_EQ(info.levels[1].ways, 2); in TEST_F()
[all …]
/aosp_15_r20/external/cpu_features/test/
H A Dcpuinfo_x86_test.cc286 EXPECT_EQ(info.levels[0].ways, 8); in TEST_F()
295 EXPECT_EQ(info.levels[1].ways, 8); in TEST_F()
303 EXPECT_EQ(info.levels[2].ways, 4); in TEST_F()
311 EXPECT_EQ(info.levels[3].ways, 12); in TEST_F()
336 EXPECT_EQ(info.levels[0].ways, 8); in TEST_F()
345 EXPECT_EQ(info.levels[1].ways, 8); in TEST_F()
353 EXPECT_EQ(info.levels[2].ways, 8); in TEST_F()
361 EXPECT_EQ(info.levels[3].ways, 12); in TEST_F()
521 EXPECT_EQ(info.levels[0].ways, 4); in TEST_F()
530 EXPECT_EQ(info.levels[1].ways, 2); in TEST_F()
[all …]
/aosp_15_r20/external/jazzer-api/src/main/java/com/code_intelligence/jazzer/api/
H A DAutofuzz.java107 * meaningful ways for a number of reasons.
137 * meaningful ways for a number of reasons.
167 * meaningful ways for a number of reasons.
197 * meaningful ways for a number of reasons.
228 * meaningful ways for a number of reasons.
259 * meaningful ways for a number of reasons.
284 * meaningful ways for a number of reasons.
309 * meaningful ways for a number of reasons.
334 * meaningful ways for a number of reasons.
360 * meaningful ways for a number of reasons.
/aosp_15_r20/external/google-cloud-java/java-retail/proto-google-cloud-retail-v2/src/main/java/com/google/cloud/retail/v2/
H A DSetInventoryRequest.java100 * following ways:
107 * the following ways:
162 * following ways:
169 * the following ways:
226 * following ways:
233 * the following ways:
862 * following ways:
869 * the following ways:
924 * following ways:
931 * the following ways:
[all …]
H A DSetInventoryRequestOrBuilder.java54 * following ways:
61 * the following ways:
113 * following ways:
120 * the following ways:
172 * following ways:
179 * the following ways:
/aosp_15_r20/external/google-cloud-java/java-retail/proto-google-cloud-retail-v2alpha/src/main/java/com/google/cloud/retail/v2alpha/
H A DSetInventoryRequest.java100 * following ways:
107 * the following ways:
163 * following ways:
170 * the following ways:
228 * following ways:
235 * the following ways:
866 * following ways:
873 * the following ways:
928 * following ways:
935 * the following ways:
[all …]
H A DSetInventoryRequestOrBuilder.java54 * following ways:
61 * the following ways:
114 * following ways:
121 * the following ways:
174 * following ways:
181 * the following ways:
/aosp_15_r20/external/google-cloud-java/java-retail/proto-google-cloud-retail-v2beta/src/main/java/com/google/cloud/retail/v2beta/
H A DSetInventoryRequest.java100 * following ways:
107 * the following ways:
163 * following ways:
170 * the following ways:
228 * following ways:
235 * the following ways:
866 * following ways:
873 * the following ways:
928 * following ways:
935 * the following ways:
[all …]
H A DSetInventoryRequestOrBuilder.java54 * following ways:
61 * the following ways:
114 * following ways:
121 * the following ways:
174 * following ways:
181 * the following ways:
/aosp_15_r20/external/mesa3d/src/intel/common/
H A Dintel_pixel_hash.h68 * previous 3-way hash table function to an arbitrary number of ways
79 /* If both masks are equal all ways are expected to show up with in intel_compute_pixel_hash_table_nway()
87 * indices given by the bits set on the mask arguments. Ways in intel_compute_pixel_hash_table_nway()
137 * single mask is present (which means that all ways are expected in intel_compute_pixel_hash_table_nway()
141 * In cases where some ways have twice the frequency of the others, in intel_compute_pixel_hash_table_nway()
153 * since ways that appear duplicated in the phys_ids mapping above in intel_compute_pixel_hash_table_nway()
159 * number of ways. in intel_compute_pixel_hash_table_nway()
/aosp_15_r20/system/update_engine/common/
H A Dmetrics_constants.h38 // Possible ways a device can react to a new update being available.
51 // The possible ways that downloading from a HTTP or HTTPS server can fail.
92 // Possible ways an update attempt can end.
116 // Possible ways the device is connected to the Internet.
134 // Possible ways a rollback can end.
/aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/
H A DMemoryMapDataHob.h250 UINT8 ways; // Interleave ways for SAD member
253 …UINT8 NmChWays; // Channel Interleave ways for SAD. Represents channelInterBitmap ways …
254 …UINT8 FmChWays; // Channel Interleave ways for SAD. Represents FMchannelInterBitmap way…
/aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/graniterapids/ap/
H A DMemoryMapDataHob.h247 UINT8 ways; // Interleave ways for SAD member
250 …UINT8 NmChWays; // Channel Interleave ways for SAD. Represents channelInterBitmap ways …
251 …UINT8 FmChWays; // Channel Interleave ways for SAD. Represents FMchannelInterBitmap way…
/aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/
H A DMemoryMapDataHob.h247 UINT8 ways; // Interleave ways for SAD member
250 …UINT8 NmChWays; // Channel Interleave ways for SAD. Represents channelInterBitmap ways …
251 …UINT8 FmChWays; // Channel Interleave ways for SAD. Represents FMchannelInterBitmap way…
/aosp_15_r20/device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/
Dcore_cm7.h1937 uint32_t sets, ways; in SCB_EnableDCache() local
1942 ways = CCSIDR_WAYS(ccsidr); in SCB_EnableDCache()
1943 wshift = __CLZ(ways) & 0x1f; in SCB_EnableDCache()
1948 int32_t tmpways = ways; in SCB_EnableDCache()
1972 uint32_t sets, ways; in SCB_DisableDCache() local
1977 ways = CCSIDR_WAYS(ccsidr); in SCB_DisableDCache()
1978 wshift = __CLZ(ways) & 0x1f; in SCB_DisableDCache()
1985 int32_t tmpways = ways; in SCB_DisableDCache()
2007 uint32_t sets, ways; in SCB_InvalidateDCache() local
2012 ways = CCSIDR_WAYS(ccsidr); in SCB_InvalidateDCache()
[all …]
/aosp_15_r20/external/coreboot/src/soc/intel/common/block/cpu/car/
H A Dcache_as_ram.S470 * (Line_Size + 1) * (Sets + 1) * (Partitions + 1) * (Ways + 1)
491 * The number of the ways that we want to protect from eviction
493 * size is Total LLC size / Total number of LLC ways.
510 * ways to be configured for non-eviction
521 mov %ebx, %edi /* back up number of ways */
573 /* Set MSR 0xC85 L3_Protected_ways = ((1 << data ways) - 1) */
/aosp_15_r20/external/googleapis/google/bigtable/admin/v2/
H A Dbigtable_table_admin.proto72 // feature might be changed in backward-incompatible ways and is not
246 // feature might be changed in backward-incompatible ways and is not
267 // feature might be changed in backward-incompatible ways and is not
281 // feature might be changed in backward-incompatible ways and is not
295 // feature might be changed in backward-incompatible ways and is not
562 // feature might be changed in backward-incompatible ways and is not recommended
876 // feature might be changed in backward-incompatible ways and is not recommended
920 // feature might be changed in backward-incompatible ways and is not recommended
939 // feature might be changed in backward-incompatible ways and is not recommended
967 // feature might be changed in backward-incompatible ways and is not recommended
[all …]
/aosp_15_r20/external/coreboot/src/vendorcode/cavium/include/bdk/libbdk-arch/
H A Dbdk-csrs-mio_fus.h1178 0x1 = 3/4 ways (12-way, 1.5 MB).
1179 0x2 = 1/2 ways (8-way, 1 MB).
1180 0x3 = 1/4 ways (4-way, 512 KB).
1229 0x1 = 3/4 ways (12-way, 1.5 MB).
1230 0x2 = 1/2 ways (8-way, 1 MB).
1231 0x3 = 1/4 ways (4-way, 512 KB).
1270 0x1 = 3/4 ways (12-way, 1.5 MB).
1271 0x2 = 1/2 ways (8-way, 1 MB).
1272 0x3 = 1/4 ways (4-way, 512 KB).
1325 0x1 = 3/4 ways (12-way, 1.5 MB).
[all …]

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