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/linux-6.14.4/arch/arm64/boot/dts/rockchip/
Drk3568-radxa-e25.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
4 #include "rk3568-radxa-cm3i.dtsi"
14 pwm-leds {
15 compatible = "pwm-leds-multicolor";
17 multi-led {
20 max-brightness = <255>;
22 led-red {
27 led-green {
32 led-blue {
[all …]
Drk3588-coolpi-cm5-evb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/soc/rockchip,vop2.h>
11 #include "rk3588-coolpi-cm5.dtsi"
15 compatible = "coolpi,pi-cm5-evb", "coolpi,pi-cm5", "rockchip,rk3588";
18 compatible = "pwm-backlight";
19 enable-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
20 pinctrl-names = "default";
21 pinctrl-0 = <&bl_en>;
[all …]
Drk3588-edgeble-neu6a-io.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
10 stdout-path = "serial2:1500000n8";
14 pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator {
15 compatible = "gated-fixed-clock";
16 #clock-cells = <0>;
17 clock-frequency = <100000000>;
18 clock-output-names = "pcie30_refclk";
19 vdd-supply = <&vcc3v3_pi6c_05>;
22 vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 {
[all …]
Drk3588-armsom-w3.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/leds/common.h>
7 #include "rk3588-armsom-lm7.dtsi"
18 analog-sound {
19 compatible = "audio-graph-card";
20 label = "rk3588-es8316";
30 hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
31 pinctrl-names = "default";
[all …]
Drk3588-orangepi-5-plus.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rockchip.h>
10 #include <dt-bindings/soc/rockchip,vop2.h>
11 #include <dt-bindings/usb/pd.h>
12 #include "rk3588-orangepi-5.dtsi"
16 compatible = "xunlong,orangepi-5-plus", "rockchip,rk3588";
18 hdmi0-con {
19 compatible = "hdmi-connector";
[all …]
Drk3588-ok3588-c.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
4 #include "rk3588-fet3588-c.dtsi"
7 model = "Forlinx OK3588-C Board";
8 compatible = "forlinx,ok3588-c", "forlinx,fet3588-c", "rockchip,rk3588";
16 adc-keys-0 {
17 compatible = "adc-keys";
18 io-channels = <&saradc 0>;
19 io-channel-names = "buttons";
20 keyup-threshold-microvolt = <1800000>;
[all …]
Drk3568-nanopi-r5c.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
9 /dts-v1/;
10 #include "rk3568-nanopi-r5s.dtsi"
14 compatible = "friendlyarm,nanopi-r5c", "rockchip,rk3568";
16 gpio-keys {
17 compatible = "gpio-keys";
18 pinctrl-names = "default";
19 pinctrl-0 = <&reset_button_pin>;
21 button-reset {
22 debounce-interval = <50>;
[all …]
Drk3568-nanopi-r5s.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
9 /dts-v1/;
10 #include "rk3568-nanopi-r5s.dtsi"
14 compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568";
20 gpio-leds {
21 compatible = "gpio-leds";
22 pinctrl-names = "default";
23 pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&power_led_pin>, <&wan_led_pin>;
25 led-lan1 {
28 function-enumerator = <1>;
[all …]
Drk3588s-orangepi-5.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include "rk3588s-orangepi-5.dtsi"
9 compatible = "xunlong,orangepi-5", "rockchip,rk3588s";
11 vcc3v3_pcie20: regulator-vcc3v3-pcie20 {
12 compatible = "regulator-fixed";
13 enable-active-high;
15 regulator-name = "vcc3v3_pcie20";
16 regulator-boot-on;
17 regulator-min-microvolt = <1800000>;
[all …]
Drk3588-rock-5-itx.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/pinctrl/rockchip.h>
13 #include <dt-bindings/pwm/pwm.h>
14 #include "dt-bindings/usb/pd.h"
19 compatible = "radxa,rock-5-itx", "rockchip,rk3588";
28 stdout-path = "serial2:1500000n8";
[all …]
Drk3588-friendlyelec-cm3588-nas.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/pinctrl/rockchip.h>
14 #include <dt-bindings/soc/rockchip,vop2.h>
15 #include <dt-bindings/usb/pd.h>
16 #include "rk3588-friendlyelec-cm3588.dtsi"
20 compatible = "friendlyarm,cm3588-nas", "friendlyarm,cm3588", "rockchip,rk3588";
22 adc_key_recovery: adc-key-recovery {
[all …]
Drk3588-coolpi-cm5-genbook.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/soc/rockchip,vop2.h>
11 #include "rk3588-coolpi-cm5.dtsi"
15 compatible = "coolpi,pi-cm5-genbook", "coolpi,pi-cm5", "rockchip,rk3588";
18 compatible = "pwm-backlight";
19 enable-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
20 pinctrl-names = "default";
21 pinctrl-0 = <&bl_en>;
[all …]
Drk3399-roc-pc-mezzanine.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd
7 /dts-v1/;
8 #include "rk3399-roc-pc.dtsi"
11 model = "Firefly ROC-RK3399-PC Mezzanine Board";
12 compatible = "firefly,roc-rk3399-pc-mezzanine", "rockchip,rk3399";
19 poe_12v: regulator-poe-12v {
20 compatible = "regulator-fixed";
21 regulator-name = "poe_12v";
22 regulator-always-on;
[all …]
Drk3568-fastrhino-r66s.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 /dts-v1/;
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/leds/common.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include <dt-bindings/soc/rockchip,vop2.h>
13 stdout-path = "serial2:1500000n8";
16 gpio-keys {
17 compatible = "gpio-keys";
[all …]
Drk3588-edgeble-neu6a-wifi.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * DT-overlay for Edgeble On-SoM WiFi6/BT M.2 1216 modules,
6 * - AW-XM548NF
7 * - Intel 8260D2W
10 /dts-v1/;
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/pinctrl/rockchip.h>
17 vcc3v3_pcie2x1l1: regulator-vcc3v3-pcie2x1l1 {
18 compatible = "regulator-fixed";
19 enable-active-high;
[all …]
Drk3588-nanopc-t6.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/pinctrl/rockchip.h>
13 #include <dt-bindings/soc/rockchip,vop2.h>
14 #include <dt-bindings/usb/pd.h>
18 model = "FriendlyElec NanoPC-T6";
19 compatible = "friendlyarm,nanopc-t6", "rockchip,rk3588";
26 adc-keys-0 {
[all …]
Drk3399-nanopc-t4.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * FriendlyElec NanoPC-T4 board device tree source
11 /dts-v1/;
12 #include "rk3399-nanopi4.dtsi"
15 model = "FriendlyElec NanoPC-T4";
16 compatible = "friendlyarm,nanopc-t4", "rockchip,rk3399";
18 vcc12v0_sys: regulator-vcc12v0-sys {
19 compatible = "regulator-fixed";
20 regulator-always-on;
21 regulator-boot-on;
[all …]
Drk3588-rock-5b.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/leds/common.h>
7 #include <dt-bindings/soc/rockchip,vop2.h>
12 compatible = "radxa,rock-5b", "rockchip,rk3588";
21 stdout-path = "serial2:1500000n8";
24 analog-sound {
25 compatible = "audio-graph-card";
26 label = "rk3588-es8316";
[all …]
Drk3399-nanopi-r4s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * FriendlyElec NanoPC-R4 board device tree source
15 /dts-v1/;
17 #include "rk3399-nanopi4.dtsi"
20 /delete-node/ display-subsystem;
22 gpio-leds {
23 pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
25 /delete-node/ led-0;
27 lan_led: led-lan {
32 sys_led: led-sys {
[all …]
Drk3588-rock-5b-pcie-ep.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * DT-overlay to run the PCIe3_4L Dual Mode controller in Endpoint mode
8 * tree overlay: rk3588-rock-5b-pcie-srns.dtso.
11 /dts-v1/;
15 rockchip,rx-common-refclk-mode = <0 0 0 0>;
23 vpcie3v3-supply = <&vcc3v3_pcie30>;
Drk3588-orangepi-5-compact.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include "rk3588-orangepi-5.dtsi"
11 compatible = "xunlong,orangepi-5-max", "rockchip,rk3588";
13 vcc5v0_usb30_otg: vcc5v0-usb30-otg-regulator {
14 compatible = "regulator-fixed";
15 enable-active-high;
18 pinctrl-names = "default";
[all …]
Drk3566-soquartz-blade.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
10 #include "rk3566-soquartz.dtsi"
14 compatible = "pine64,soquartz-blade", "pine64,soquartz", "rockchip,rk3566";
21 vcc3v0_sd: regulator-vcc3v0-sd {
22 compatible = "regulator-fixed";
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/pci/
Drcar-pci-host.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pci/rcar-pci-host.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas R-Car PCIe Host
11 - Marek Vasut <[email protected]>
12 - Yoshihiro Shimoda <[email protected]>
15 - $ref: /schemas/pci/pci-host-bridge.yaml#
20 - const: renesas,pcie-r8a7779 # R-Car H1
21 - items:
[all …]
Dnvidia,tegra194-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <[email protected]>
11 - Jon Hunter <[email protected]>
12 - Vidya Sagar <[email protected]>
16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
20 See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device
26 - nvidia,tegra194-pcie
[all …]
/linux-6.14.4/drivers/pci/controller/
Dpcie-rockchip-host.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Wenrui Li <wenrui.li@rock-chips.com>
37 #include "pcie-rockchip.h"
76 if (pci_is_root_bus(bus) || pci_is_root_bus(bus->parent)) in rockchip_pcie_valid_device()
87 if (rockchip->legacy_phy) in rockchip_pcie_lane_map()
88 return GENMASK(MAX_LANE_NUM - 1, 0); in rockchip_pcie_lane_map()
93 /* The link may be using a reverse-indexed mapping. */ in rockchip_pcie_lane_map()
105 addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + where; in rockchip_pcie_rd_own_conf()
132 addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + offset; in rockchip_pcie_wr_own_conf()
[all …]

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