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/linux-6.14.4/Documentation/devicetree/bindings/display/rockchip/
Drockchip-vop2.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Sandy Huang <hjc@rock-chips.com>
16 - Heiko Stuebner <[email protected]>
21 - rockchip,rk3566-vop
22 - rockchip,rk3568-vop
23 - rockchip,rk3588-vop
27 - description:
[all …]
Dcdn-dp-rockchip.txt5 - compatible: must be "rockchip,rk3399-cdn-dp"
7 - reg: physical base address of the controller and length
9 - clocks: from common clock binding: handle to dp clock.
11 - clock-names: from common clock binding:
12 Required elements: "core-clk" "pclk" "spdif" "grf"
14 - resets : a list of phandle + reset specifier pairs
15 - reset-names : string of reset names
17 - power-domains : power-domain property defined with a phandle
19 - assigned-clocks: main clock, should be <&cru SCLK_DP_CORE>
20 - assigned-clock-rates : the DP core clk frequency, shall be: 100000000
[all …]
Drockchip,dw-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Yao <[email protected]>
17 - $ref: ../bridge/synopsys,dw-hdmi.yaml#
18 - $ref: /schemas/sound/dai-common.yaml#
23 - rockchip,rk3228-dw-hdmi
24 - rockchip,rk3288-dw-hdmi
25 - rockchip,rk3328-dw-hdmi
[all …]
Drockchip,lvds.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip low-voltage differential signal (LVDS) transmitter
10 - Sandy Huang <hjc@rock-chips.com>
11 - Heiko Stuebner <[email protected]>
16 - rockchip,px30-lvds
17 - rockchip,rk3288-lvds
25 clock-names:
28 avdd1v0-supply:
[all …]
/linux-6.14.4/drivers/gpu/drm/rockchip/
Danalogix_dp-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Author: Andy Yan <andy.yan@rock-chips.com>
7 * Yakir Yang <ykk@rock-chips.com>
8 * Jeff Chen <jeff.chen@rock-chips.com>
45 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips
46 * @lcdsel_grf_reg: grf register offset of lcdc select
47 * @lcdsel_big: reg value of selecting vop big for eDP
48 * @lcdsel_lit: reg value of selecting vop little for eDP
66 struct regmap *grf; member
89 reset_control_assert(dp->rst); in rockchip_dp_pre_init()
[all …]
Drockchip_lvds.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Mark Yao <mark.yao@rock-chips.com>
6 * Sandy Huang <hjc@rock-chips.com>
38 * struct rockchip_lvds_soc_data - rockchip lvds Soc private data
50 struct regmap *grf; member
79 writel_relaxed(val, lvds->regs + offset); in rk3288_writel()
80 if (lvds->output == DISPLAY_OUTPUT_LVDS) in rk3288_writel()
82 writel_relaxed(val, lvds->regs + offset + RK3288_LVDS_CH1_OFFSET); in rk3288_writel()
87 if (strncmp(s, "jeida-18", 8) == 0) in rockchip_lvds_name_to_format()
89 else if (strncmp(s, "jeida-24", 8) == 0) in rockchip_lvds_name_to_format()
[all …]
Ddw_hdmi-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
60 * struct rockchip_hdmi_chip_data - splite the grf setting of kind of chips
61 * @lcdsel_grf_reg: grf register offset of lcdc select
62 * @lcdsel_big: reg value of selecting vop big for HDMI
63 * @lcdsel_lit: reg value of selecting vop little for HDMI
201 struct device_node *np = hdmi->dev->of_node; in rockchip_hdmi_parse_dt()
204 hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); in rockchip_hdmi_parse_dt()
205 if (IS_ERR(hdmi->regmap)) { in rockchip_hdmi_parse_dt()
206 dev_err(hdmi->dev, "Unable to get rockchip,grf\n"); in rockchip_hdmi_parse_dt()
207 return PTR_ERR(hdmi->regmap); in rockchip_hdmi_parse_dt()
[all …]
Dcdn-dp-core.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Chris Zhong <zyw@rock-chips.com>
16 #include <sound/hdmi-codec.h>
25 #include "cdn-dp-core.h"
26 #include "cdn-dp-reg.h"
61 { .compatible = "rockchip,rk3399-cdn-dp",
73 ret = clk_prepare_enable(dp->grf_clk); in cdn_dp_grf_write()
75 DRM_DEV_ERROR(dp->dev, "Failed to prepare_enable grf clock\n"); in cdn_dp_grf_write()
79 ret = regmap_write(dp->grf, reg, val); in cdn_dp_grf_write()
81 DRM_DEV_ERROR(dp->dev, "Could not write to GRF: %d\n", ret); in cdn_dp_grf_write()
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/soc/rockchip/
Dgrf.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/soc/rockchip/grf.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip General Register Files (GRF)
10 - Heiko Stuebner <[email protected]>
15 - items:
16 - enum:
17 - rockchip,rk3288-sgrf
18 - rockchip,rk3566-pipe-grf
[all …]
/linux-6.14.4/arch/arm64/boot/dts/rockchip/
Drk3566-base.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include "rk356x-base.dtsi"
10 compatible = "rockchip,rk3566-pipe-grf", "syscon";
14 power-domain@RK3568_PD_PIPE {
22 #power-domain-cells = <0>;
28 phy-names = "usb2-phy";
30 maximum-speed = "high-speed";
33 &vop {
34 compatible = "rockchip,rk3566-vop";
Drk3568.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "rk356x-base.dtsi"
11 cpu0_opp_table: opp-table-0 {
12 compatible = "operating-points-v2";
13 opp-shared;
15 opp-408000000 {
16 opp-hz = /bits/ 64 <408000000>;
17 opp-microvolt = <850000 850000 1150000>;
18 clock-latency-ns = <40000>;
21 opp-600000000 {
[all …]
Drk3588-base.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/power/rk3588-power.h>
10 #include <dt-bindings/reset/rockchip,rk3588-cru.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/ata/ahci.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
[all …]
Drk356x-base.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3568-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3568-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
[all …]
Drk3399-base.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3399-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3399-power.h>
12 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
[all …]
Dpx30.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/px30-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/px30-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
[all …]
Drk3328.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3328-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3328-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
[all …]
/linux-6.14.4/arch/arm/boot/dts/rockchip/
Drk3066a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3066a-cru.h>
10 #include <dt-bindings/power/rk3066-power.h>
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "rockchip,rk3066-smp";
28 compatible = "arm,cortex-a9";
29 next-level-cache = <&L2>;
[all …]
Drv1126.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rv1126-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rockchip,rv1126-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
[all …]
Drk3188.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3188-cru.h>
10 #include <dt-bindings/power/rk3188-power.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
19 enable-method = "rockchip,rk3066-smp";
23 compatible = "arm,cortex-a9";
24 next-level-cache = <&L2>;
[all …]
Drk3036.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3036-cru.h>
8 #include <dt-bindings/soc/rockchip,boot-mode.h>
9 #include <dt-bindings/power/rk3036-power.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
[all …]
Drk3288.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power/rk3288-power.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #address-cells = <2>;
[all …]
Drk3128.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/rk3128-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3128-power.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
[all …]
Drk322x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3228-cru.h>
8 #include <dt-bindings/thermal/thermal.h>
9 #include <dt-bindings/power/rk3228-power.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
[all …]
/linux-6.14.4/drivers/soc/rockchip/
Dio-domain.c1 // SPDX-License-Identifier: GPL-2.0-only
26 * - If the voltage on a rail is above the "1.8" voltage (1.98V) we'll tell the
28 * - If the voltage on a rail is above the "3.3" voltage (3.6V) we'll consider
80 struct regmap *grf; member
88 struct rockchip_iodomain *iod = supply->iod; in rk3568_iodomain_write()
93 switch (supply->idx) { in rk3568_iodomain_write()
97 b = supply->idx; in rk3568_iodomain_write()
99 b = supply->idx + 4; in rk3568_iodomain_write()
102 regmap_write(iod->grf, RK3568_PMU_GRF_IO_VSEL2, val0); in rk3568_iodomain_write()
103 regmap_write(iod->grf, RK3568_PMU_GRF_IO_VSEL2, val1); in rk3568_iodomain_write()
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/power/
Drockchip-io-domain.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/rockchip-io-domain.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <[email protected]>
23 General Register File (GRF) in sync with the actual value of a voltage
42 to report their voltage. The IO Voltage Domain for any non-specified
48 - rockchip,px30-io-voltage-domain
49 - rockchip,px30-pmu-io-voltage-domain
50 - rockchip,rk3188-io-voltage-domain
[all …]

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