| /linux-6.14.4/drivers/clk/mediatek/ |
| D | clk-mt6735-pericfg.c | 47 GATE_MTK(CLK_PERI_UART0, "uart0", "uart_sel", &peri_cg_regs, 17, &mtk_clk_gate_ops_setclr),
48 GATE_MTK(CLK_PERI_UART1, "uart1", "uart_sel", &peri_cg_regs, 18, &mtk_clk_gate_ops_setclr),
49 GATE_MTK(CLK_PERI_UART2, "uart2", "uart_sel", &peri_cg_regs, 19, &mtk_clk_gate_ops_setclr),
50 GATE_MTK(CLK_PERI_UART3, "uart3", "uart_sel", &peri_cg_regs, 20, &mtk_clk_gate_ops_setclr),
51 GATE_MTK(CLK_PERI_UART4, "uart4", "uart_sel", &peri_cg_regs, 21, &mtk_clk_gate_ops_setclr),
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| D | clk-mt2712.c | 656 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x060, 8, 1, 15),
901 GATE_PERI0(CLK_PERI_UART0, "per_uart0", "uart_sel", 20),
902 GATE_PERI0(CLK_PERI_UART1, "per_uart1", "uart_sel", 21),
903 GATE_PERI0(CLK_PERI_UART2, "per_uart2", "uart_sel", 22),
904 GATE_PERI0(CLK_PERI_UART3, "per_uart3", "uart_sel", 23),
918 GATE_PERI1(CLK_PERI_UART4, "per_uart4", "uart_sel", 9),
919 GATE_PERI1(CLK_PERI_SFLASH, "per_sflash", "uart_sel", 11),
920 GATE_PERI1(CLK_PERI_GMAC, "per_gmac", "uart_sel", 12),
921 GATE_PERI1(CLK_PERI_PCIE0, "per_pcie0", "uart_sel", 14),
922 GATE_PERI1(CLK_PERI_PCIE1, "per_pcie1", "uart_sel", 15),
[all …]
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| D | clk-mt7988-infracfg.c | 25 "uart_sel" };
28 "uart_sel" };
31 "uart_sel" };
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| D | clk-mt6797.c | 338 MUX_GATE(CLK_TOP_MUX_UART, "uart_sel", uart_parents, 0x0060, 8, 1, 15),
467 GATE_ICG0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22),
468 GATE_ICG0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23),
469 GATE_ICG0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24),
470 GATE_ICG0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25),
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| D | clk-mt8365.c | 429 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x060,
690 GATE_IFR2(CLK_IFR_UART0, "ifr_uart0", "uart_sel", 22),
691 GATE_IFR2(CLK_IFR_UART1, "ifr_uart1", "uart_sel", 23),
692 GATE_IFR2(CLK_IFR_UART2, "ifr_uart2", "uart_sel", 24),
693 GATE_IFR2(CLK_IFR_DSP_UART, "ifr_dsp_uart", "uart_sel", 26),
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| D | clk-mt8183.c | 491 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_UART, "uart_sel",
719 GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22),
720 GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23),
721 GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24),
722 GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25),
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| D | clk-mt8192.c | 598 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel",
806 GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", "uart_sel", 22),
807 GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23),
808 GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", "uart_sel", 24),
809 GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3", "uart_sel", 25),
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| D | clk-mt6779.c | 684 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "uart_sel", uart_parents,
924 "uart_sel", 22),
926 "uart_sel", 23),
928 "uart_sel", 24),
930 "uart_sel", 25),
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| D | clk-mt8173-pericfg.c | 38 "uart_sel",
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| D | clk-mt7981-topckgen.c | 70 FACTOR(CLK_TOP_UART_BCK, "uart_bck", "uart_sel", 1, 1),
301 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
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| D | clk-mt6795-pericfg.c | 29 "uart_sel",
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| D | clk-mt8135.c | 375 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0150, 24, 2, 31),
496 "uart_sel",
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| D | clk-mt7986-infracfg.c | 25 "uart_sel" };
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| D | clk-mt7981-infracfg.c | 27 "uart_sel" };
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| D | clk-mt7986-topckgen.c | 184 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010,
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| D | clk-mt6735-topckgen.c | 343 …MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_sel_parents, CLK_CFG_2, CLK_CFG_2_SET, CLK…
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| D | clk-mt2701.c | 504 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
873 "uart_sel",
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| D | clk-mt6765.c | 141 FACTOR(CLK_TOP_F_FUART, "f_fuart_ck", "uart_sel", 1, 1),
402 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
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| D | clk-mt7622.c | 406 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
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| D | clk-mt6795-topckgen.c | 466 TOP_MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x60, 8, 1, 15, 0),
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| /linux-6.14.4/drivers/clk/imx/ |
| D | clk-imx35.c | 65 /* 9 */ ipg, arm_per_div, ahb_per_div, ipg_per, uart_sel, uart_div, enumerator
138 clk[uart_sel] = imx_clk_mux("uart_sel", base + MX35_CCM_PDR3, 14, 1, std_sel, ARRAY_SIZE(std_sel)); in _mx35_clocks_init()
139 clk[uart_div] = imx_clk_divider("uart_div", "uart_sel", base + MX35_CCM_PDR4, 10, 6); in _mx35_clocks_init()
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| D | clk-imx6sll.c | 209 …hws[IMX6SLL_CLK_UART_SEL] = imx_clk_hw_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE… in imx6sll_clocks_init()
229 hws[IMX6SLL_CLK_UART_PODF] = imx_clk_hw_divider("uart_podf", "uart_sel", base + 0x24, 0, 6); in imx6sll_clocks_init()
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| D | clk-imx6sl.c | 322 …hws[IMX6SL_CLK_UART_SEL] = imx_clk_hw_mux("uart_sel", base + 0x24, 6, 1, uart_sel… in imx6sl_clocks_init()
361 …hws[IMX6SL_CLK_UART_ROOT] = imx_clk_hw_divider("uart_root", "uart_sel", b… in imx6sl_clocks_init()
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| D | clk-imx5.c | 157 clk[IMX5_CLK_UART_SEL] = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2, in mx5_clocks_common_init()
159 clk[IMX5_CLK_UART_PRED] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3); in mx5_clocks_common_init()
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| /linux-6.14.4/Documentation/devicetree/bindings/clock/ |
| D | imx35-clock.yaml | 32 uart_sel 13
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