Searched +full:uart +full:- +full:r1p8 (Results 1 – 4 of 4) sorted by relevance
| /linux-6.14.4/Documentation/devicetree/bindings/serial/ |
| D | cdns,uart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/cdns,uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence UART Controller
10 - Michal Simek <[email protected]>
15 - description: UART controller for Zynq-7xxx SoC
17 - const: xlnx,xuartps
18 - const: cdns,uart-r1p8
19 - description: UART controller for Zynq Ultrascale+ MPSoC
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| /linux-6.14.4/arch/xtensa/boot/dts/ |
| D | csp.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 compatible = "cdns,xtensa-xtfpga";
6 #address-cells = <1>;
7 #size-cells = <1>;
8 interrupt-parent = <&pic>;
20 #address-cells = <1>;
21 #size-cells = <0>;
23 compatible = "cdns,xtensa-cpu";
29 compatible = "cdns,xtensa-pic";
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| /linux-6.14.4/arch/arm/boot/dts/xilinx/ |
| D | zynq-7000.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "xlnx,zynq-7000";
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,cortex-a9";
20 clock-latency = <1000>;
21 cpu0-supply = <®ulator_vccpint>;
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| /linux-6.14.4/drivers/tty/serial/ |
| D | xilinx_uartps.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Cadence UART driver (found in Xilinx Zynq)
5 * Copyright (c) 2011 - 2014 Xilinx, Inc.
7 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
42 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
47 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
49 /* Register offsets for the UART. */
90 #define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
190 * struct cdns_uart - device data
191 * @port: Pointer to the UART port
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