Searched +full:thead +full:- +full:extension +full:- +full:spec (Results 1 – 3 of 3) sorted by relevance
| /linux-6.14.4/Documentation/devicetree/bindings/riscv/ |
| D | extensions.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <[email protected]>
11 - Palmer Dabbelt <[email protected]>
12 - Conor Dooley <[email protected]>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
19 given extension.
[all …]
|
| /linux-6.14.4/arch/riscv/kernel/ |
| D | cpufeature.c | 1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <asm/text-patching.h>
30 #include <asm/vendor_extensions/thead.h>
32 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
41 /* Per-cpu ISA extensions. */
47 * riscv_isa_extension_base() - Get base extension word
50 * Return: base extension word as unsigned long value
63 * __riscv_isa_extension_available() - Check whether given extension
67 * @bit: bit position of the desired extension
87 pr_err("Zicbom detected in ISA string, disabling as no cbom-block-size found\n"); in riscv_ext_zicbom_validate()
[all …]
|
| /linux-6.14.4/Documentation/arch/riscv/ |
| D | hwprobe.rst | 1 .. SPDX-License-Identifier: GPL-2.0
3 RISC-V Hardware Probing Interface
4 ---------------------------------
6 The RISC-V hardware probing interface is based around a single syscall, which
18 The arguments are split into three groups: an array of key-value pairs, a CPU
19 set, and some flags. The key-value pairs are supplied with a count. Userspace
22 will be cleared to -1, and its value set to 0. The CPU set is defined by
23 CPU_SET(3) with size ``cpusetsize`` bytes. For value-like keys (eg. vendor,
25 have the same value. Otherwise -1 will be returned. For boolean-like keys, the
33 by sys_riscv_hwprobe() to only those which match each of the key-value pairs.
[all …]
|