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/aosp_15_r20/external/llvm/test/Transforms/SimplifyCFG/X86/
H A Dswitch_to_lookup_table.ll34 switch i32 %c, label %sw.default [
36 i32 43, label %sw.bb1
37 i32 44, label %sw.bb2
38 i32 45, label %sw.bb3
39 i32 46, label %sw.bb4
40 i32 47, label %sw.bb5
41 i32 48, label %sw.bb6
44 sw.bb1: br label %return
45 sw.bb2: br label %return
46 sw.bb3: br label %return
[all …]
/aosp_15_r20/external/libvpx/vpx_dsp/mips/
H A Dintrapred16_dspr2.c55 "sw %[tmp1], (%[dst]) \n\t" in vpx_h_predictor_16x16_dspr2()
56 "sw %[tmp1], 4(%[dst]) \n\t" in vpx_h_predictor_16x16_dspr2()
57 "sw %[tmp1], 8(%[dst]) \n\t" in vpx_h_predictor_16x16_dspr2()
58 "sw %[tmp1], 12(%[dst]) \n\t" in vpx_h_predictor_16x16_dspr2()
61 "sw %[tmp2], (%[dst]) \n\t" in vpx_h_predictor_16x16_dspr2()
62 "sw %[tmp2], 4(%[dst]) \n\t" in vpx_h_predictor_16x16_dspr2()
63 "sw %[tmp2], 8(%[dst]) \n\t" in vpx_h_predictor_16x16_dspr2()
64 "sw %[tmp2], 12(%[dst]) \n\t" in vpx_h_predictor_16x16_dspr2()
67 "sw %[tmp3], (%[dst]) \n\t" in vpx_h_predictor_16x16_dspr2()
68 "sw %[tmp3], 4(%[dst]) \n\t" in vpx_h_predictor_16x16_dspr2()
[all …]
/aosp_15_r20/external/llvm/test/CodeGen/WebAssembly/
H A Dswitch.ll41 switch i32 %n, label %sw.epilog [
42 i32 0, label %sw.bb
43 i32 1, label %sw.bb
44 i32 2, label %sw.bb
45 i32 3, label %sw.bb
46 i32 4, label %sw.bb
47 i32 5, label %sw.bb
48 i32 6, label %sw.bb
49 i32 7, label %sw.bb.1
50 i32 8, label %sw.bb.1
[all …]
/aosp_15_r20/external/llvm/test/CodeGen/X86/
H A Dswitch-edge-weight.ll9 switch i32 %x, label %sw.default [
10 i32 1, label %sw.bb
11 i32 155, label %sw.bb
12 i32 156, label %sw.bb
13 i32 157, label %sw.bb
14 i32 158, label %sw.bb
15 i32 159, label %sw.bb
16 i32 1134, label %sw.bb
17 i32 1140, label %sw.bb
20 sw.bb:
[all …]
H A Dswitch-bt.ll22 switch i32 %conv, label %sw.default [
23 i32 62, label %sw.bb
24 i32 60, label %sw.bb
25 i32 38, label %sw.bb2
26 i32 94, label %sw.bb2
27 i32 61, label %sw.bb2
28 i32 33, label %sw.bb4
31 sw.bb: ; preds = %entry, %entry
33 br label %sw.epilog
35 sw.bb2: ; preds = %entry, %entry, %entry
[all …]
H A Dlea-opt.ll20 switch i32 %add, label %sw.epilog [
21 i32 1, label %sw.bb.1
22 i32 2, label %sw.bb.2
25 sw.bb.1: ; preds = %entry
28 br label %sw.epilog
30 sw.bb.2: ; preds = %entry
33 br label %sw.epilog
35 sw.epilog: ; preds = %sw.bb.2, %sw.bb.1, %entry
62 switch i32 %add, label %sw.epilog [
63 i32 1, label %sw.bb.1
[all …]
/aosp_15_r20/external/llvm/test/CodeGen/ARM/
H A D2011-08-25-ldmia_ret.ll6 ; into sw.bb18 resulting in an ldmia_ret in the middle of the
20 br i1 %call, label %sw.bb18, label %sw.bb2
22 sw.bb2: ; preds = %entry
24 br i1 %cmp, label %sw.epilog58, label %land.lhs.true
26 land.lhs.true: ; preds = %sw.bb2
28 br i1 %cmp13, label %if.then, label %sw.epilog58
32 br label %sw.epilog58
46 sw.bb18:
48 switch i32 %call20, label %sw.default56 [
49 i32 168, label %sw.bb21
[all …]
/aosp_15_r20/prebuilts/go/linux-x86/src/net/internal/socktest/
Dsys_windows.go13 func (sw *Switch) WSASocket(family, sotype, proto int32, protinfo *syscall.WSAProtocolInfo, group u…
14 sw.once.Do(sw.init)
17 sw.fmu.RLock()
18 f, _ := sw.fltab[FilterSocket]
19 sw.fmu.RUnlock()
33 sw.smu.Lock()
34 defer sw.smu.Unlock()
36 sw.stats.getLocked(so.Cookie).OpenFailed++
39 nso := sw.addLocked(s, int(family), int(sotype), int(proto))
40 sw.stats.getLocked(nso.Cookie).Opened++
[all …]
Dsys_unix.go12 func (sw *Switch) Socket(family, sotype, proto int) (s int, err error) {
13 sw.once.Do(sw.init)
16 sw.fmu.RLock()
17 f := sw.fltab[FilterSocket]
18 sw.fmu.RUnlock()
32 sw.smu.Lock()
33 defer sw.smu.Unlock()
35 sw.stats.getLocked(so.Cookie).OpenFailed++
38 nso := sw.addLocked(s, family, sotype, proto)
39 sw.stats.getLocked(nso.Cookie).Opened++
[all …]
/aosp_15_r20/external/llvm/test/Transforms/InstCombine/
H A Dnarrow-switch.ll13 ; ALL-NEXT: i32 100, label %sw.bb1
14 ; ALL-NEXT: i32 1001, label %sw.bb2
19 switch i64 %and, label %sw.default [
21 i64 100, label %sw.bb1
22 i64 1001, label %sw.bb2
25 sw.bb1:
28 sw.bb2:
31 sw.default:
35 %retval.0 = phi i32 [ 24, %sw.default ], [ 123, %sw.bb2 ], [ 213, %sw.bb1 ], [ 231, %entry ]
43 ; ALL-NEXT: i32 -100, label %sw.bb1
[all …]
/aosp_15_r20/external/llvm/test/Transforms/SimplifyCFG/
H A Dpreserve-branchweights-switch-create.ll49 i32 2, label %sw.bb
50 i32 3, label %sw.bb1
53 ; CHECK: switch i32 %N, label %sw.epilog
54 ; CHECK: i32 2, label %sw.bb
55 ; CHECK: i32 3, label %sw.bb1
56 ; CHECK: i32 4, label %sw.bb5
59 sw.bb:
61 br label %sw.epilog
63 sw.bb1:
65 br label %sw.epilog
[all …]
/aosp_15_r20/external/llvm/test/Transforms/CodeGenPrepare/AArch64/
H A Dwiden_switch.ll10 switch i16 %trunc, label %sw.default [
11 i16 1, label %sw.bb0
12 i16 -1, label %sw.bb1
15 sw.bb0:
18 sw.bb1:
21 sw.default:
25 %retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
30 ; ARM64-NEXT: switch i32 %0, label %sw.default [
32 ; ARM64-NEXT: i32 65535, label %sw.bb1
40 switch i17 %trunc, label %sw.default [
[all …]
/aosp_15_r20/external/llvm/test/Transforms/CodeGenPrepare/X86/
H A Dwiden_switch.ll10 switch i16 %trunc, label %sw.default [
11 i16 1, label %sw.bb0
12 i16 -1, label %sw.bb1
15 sw.bb0:
18 sw.bb1:
21 sw.default:
25 %retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
30 ; X86-NEXT: switch i16 %trunc, label %sw.default [
32 ; X86-NEXT: i16 -1, label %sw.bb1
40 switch i17 %trunc, label %sw.default [
[all …]
/aosp_15_r20/external/llvm/test/CodeGen/Mips/
H A Djtstat.ll12 switch i32 %0, label %sw.epilog [
13 i32 115, label %sw.bb
14 i32 105, label %sw.bb1
15 i32 100, label %sw.bb2
16 i32 108, label %sw.bb3
17 i32 99, label %sw.bb4
18 i32 68, label %sw.bb5
19 i32 81, label %sw.bb6
20 i32 76, label %sw.bb7
23 sw.bb: ; preds = %entry
[all …]
H A Dinterrupt-attr.ll6 ; CHECK: sw $27, [[R1:[0-9]+]]($sp)
8 ; CHECK: sw $27, [[R2:[0-9]+]]($sp)
14 ; CHECK: sw $7, {{[0-9]+}}($sp)
15 ; CHECK: sw $6, {{[0-9]+}}($sp)
16 ; CHECK: sw $5, {{[0-9]+}}($sp)
17 ; CHECK: sw $4, {{[0-9]+}}($sp)
18 ; CHECK: sw $3, {{[0-9]+}}($sp)
19 ; CHECK: sw $2, {{[0-9]+}}($sp)
20 ; CHECK: sw $25, {{[0-9]+}}($sp)
21 ; CHECK: sw $24, {{[0-9]+}}($sp)
[all …]
/aosp_15_r20/external/tensorflow/tensorflow/python/summary/writer/
H A Dwriter_test.py105 sw = self._FileWriter(test_dir)
107 sw.add_session_log(event_pb2.SessionLog(status=SessionLog.START), 1)
108 sw.add_summary(
113 sw.add_summary(
120 sw.add_graph(g, global_step=30)
125 sw.add_run_metadata(run_metadata, "test run", global_step=40)
126 sw.close()
181 sw = self._FileWriter(test_dir, graph=g)
182 sw.close()
190 sw = self._FileWriter(test_dir, g)
[all …]
/aosp_15_r20/external/swiftshader/tests/PipelineBenchmarks/
H A DPipelineBenchmarks.cpp33 namespace sw { namespace
102 BENCHMARK_CAPTURE(Transcendental1, sw_Sin_highp, LIFT(sw::Sin), false /* relaxedPrecision */)->Arg(…
103 BENCHMARK_CAPTURE(Transcendental1, sw_Sin_mediump, LIFT(sw::Sin), true /* relaxedPrecision */)->Arg…
105 BENCHMARK_CAPTURE(Transcendental1, sw_Cos_highp, LIFT(sw::Cos), false /* relaxedPrecision */)->Arg(…
106 BENCHMARK_CAPTURE(Transcendental1, sw_Cos_mediump, LIFT(sw::Cos), true /* relaxedPrecision */)->Arg…
108 BENCHMARK_CAPTURE(Transcendental1, sw_Tan_highp, LIFT(sw::Tan), false /* relaxedPrecision */)->Arg(…
109 BENCHMARK_CAPTURE(Transcendental1, sw_Tan_mediump, LIFT(sw::Tan), true /* relaxedPrecision */)->Arg…
112 BENCHMARK_CAPTURE(Transcendental1, sw_Asin_highp, LIFT(sw::Asin), false /* relaxedPrecision */)->Ar…
113 BENCHMARK_CAPTURE(Transcendental1, sw_Asin_mediump, LIFT(sw::Asin), true /* relaxedPrecision */)->A…
115 BENCHMARK_CAPTURE(Transcendental1, sw_Acos_highp, LIFT(sw::Acos), false /* relaxedPrecision */)->Ar…
[all …]
/aosp_15_r20/external/llvm/test/CodeGen/PowerPC/
H A Dpr22711.ll13 switch i32 %1, label %sw.epilog [
14 i32 17, label %sw.bb
15 i32 13, label %sw.bb1
16 i32 11, label %sw.bb2
17 i32 7, label %sw.bb3
18 i32 5, label %sw.bb4
19 i32 3, label %sw.bb5
20 i32 2, label %sw.bb6
23 sw.bb: ; preds = %entry
26 br label %sw.epilog
[all …]
/aosp_15_r20/external/swiftshader/src/Pipeline/
H A DSpirvShaderDebug.hpp53 struct PrintValue::Ty<sw::Spirv::Object::ID>
55 …static inline std::string fmt(sw::Spirv::Object::ID v) { return "Object<" + std::to_string(v.value… in fmt()
56 static inline std::vector<Value *> val(sw::Spirv::Object::ID v) { return {}; } in val()
59 struct PrintValue::Ty<sw::Spirv::Type::ID>
61 …static inline std::string fmt(sw::Spirv::Type::ID v) { return "Type<" + std::to_string(v.value()) … in fmt()
62 static inline std::vector<Value *> val(sw::Spirv::Type::ID v) { return {}; } in val()
65 struct PrintValue::Ty<sw::Spirv::Block::ID>
67 …static inline std::string fmt(sw::Spirv::Block::ID v) { return "Block<" + std::to_string(v.value()… in fmt()
68 static inline std::vector<Value *> val(sw::Spirv::Block::ID v) { return {}; } in val()
72 struct PrintValue::Ty<sw::Intermediate>
[all …]
/aosp_15_r20/external/llvm/test/Instrumentation/SanitizerCoverage/
H A Dswitch-tracing.ll12 switch i32 %x, label %sw.epilog [
13 i32 1, label %sw.bb
14 i32 101, label %sw.bb.1
15 i32 1001, label %sw.bb.2
18 sw.bb: ; preds = %entry
20 br label %sw.epilog
22 sw.bb.1: ; preds = %entry
24 br label %sw.epilog
26 sw.bb.2: ; preds = %entry
28 br label %sw.epilog
[all …]
/aosp_15_r20/external/llvm/test/CodeGen/Mips/cconv/
H A Darguments-varargs.ll28 ; O32-DAG: sw $7, 20([[SP]])
29 ; O32-DAG: sw $6, 16([[SP]])
30 ; O32-DAG: sw $5, 12([[SP]])
47 ; O32-DAG: sw [[VA]], 0([[SP]])
50 ; N32-DAG: sw [[VA]], 0([[SP]])
56 ; O32-DAG: sw [[VA]], 0([[SP]])
63 ; O32-DAG: sw [[VA2]], 0([[SP]])
67 ; N32-DAG: sw [[VA2]], 0([[SP]])
97 ; O32-DAG: sw [[VA2]], 0([[SP]])
101 ; N32-DAG: sw [[VA3]], 0([[SP]])
[all …]
/aosp_15_r20/external/llvm/test/CodeGen/Hexagon/
H A Dpic-jumptables.ll10 switch i32 %y, label %sw.epilog [
11 i32 1, label %sw.bb
12 i32 2, label %sw.bb1
13 i32 3, label %sw.bb2
14 i32 4, label %sw.bb3
15 i32 5, label %sw.bb4
18 sw.bb: ; preds = %entry
20 br label %sw.epilog
22 sw.bb1: ; preds = %entry
24 br label %sw.epilog
[all …]
/aosp_15_r20/external/libaom/third_party/libyuv/source/
H A Drow_mips.cc90 "sw $t0, 0(%[dst]) \n" in CopyRow_MIPS()
91 "sw $t1, 4(%[dst]) \n" in CopyRow_MIPS()
92 "sw $t2, 8(%[dst]) \n" in CopyRow_MIPS()
93 "sw $t3, 12(%[dst]) \n" in CopyRow_MIPS()
94 "sw $t4, 16(%[dst]) \n" in CopyRow_MIPS()
95 "sw $t5, 20(%[dst]) \n" in CopyRow_MIPS()
96 "sw $t6, 24(%[dst]) \n" in CopyRow_MIPS()
97 "sw $t7, 28(%[dst]) \n" in CopyRow_MIPS()
111 "sw $t0, 32(%[dst]) \n" in CopyRow_MIPS()
112 "sw $t1, 36(%[dst]) \n" in CopyRow_MIPS()
[all …]
/aosp_15_r20/external/llvm/test/Transforms/Util/MemorySSA/
H A Dmany-dom-backedge.ll14 ; CHECK: 9 = MemoryPhi({entry,liveOnEntry},{sw.epilog,6})
16 %n = phi i32 [ 0, %entry ], [ %1, %sw.epilog ]
18 switch i32 %n, label %sw.default [
19 i32 0, label %sw.bb
20 i32 1, label %sw.bb1
21 i32 2, label %sw.bb2
22 i32 3, label %sw.bb3
25 sw.bb:
29 br label %sw.epilog
31 sw.bb1:
[all …]
/aosp_15_r20/external/llvm/tools/llvm-readobj/
H A DARMEHABIPrinter.h30 ScopedPrinter &SW; variable
67 OpcodeDecoder(ScopedPrinter &SW) : SW(SW), OS(SW.getOStream()) {} in OpcodeDecoder() argument
98 SW.startLine() << format("0x%02X ; vsp = vsp + %u\n", Opcode, in Decode_00xxxxxx()
103 SW.startLine() << format("0x%02X ; vsp = vsp - %u\n", Opcode, in Decode_01xxxxxx()
112 SW.startLine() in Decode_1000iiii_iiiiiiii()
121 SW.startLine() << format("0x%02X ; reserved (ARM MOVrr)\n", Opcode); in Decode_10011101()
125 SW.startLine() << format("0x%02X ; reserved (WiMMX MOVrr)\n", Opcode); in Decode_10011111()
129 SW.startLine() << format("0x%02X ; vsp = r%u\n", Opcode, (Opcode & 0x0f)); in Decode_1001nnnn()
133 SW.startLine() << format("0x%02X ; pop ", Opcode); in Decode_10100nnn()
139 SW.startLine() << format("0x%02X ; pop ", Opcode); in Decode_10101nnn()
[all …]

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