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/linux-6.14.4/Documentation/devicetree/bindings/soc/loongson/
Dloongson,ls2k-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/loongson/loongson,ls2k-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson-2 Power Manager controller
10 - Yinbo Zhu <[email protected]>
15 - items:
16 - const: loongson,ls2k0500-pmc
17 - const: syscon
18 - items:
[all …]
/linux-6.14.4/drivers/acpi/
Dacpi_fpdt.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * FPDT support for exporting boot and suspend/resume performance data
19 * performance data fields, for boot or suspend or resume phase.
31 u64 address; /* physical address of the S3PT/FBPT table */ member
83 return sprintf(buf, "%llu\n", record_##phase->name); \
90 FPDT_ATTR(suspend, suspend_start);
91 FPDT_ATTR(suspend, suspend_end);
101 return sprintf(buf, "%u\n", record_resume->resume_count); in resume_count_show()
127 .name = "suspend",
148 static bool fpdt_address_valid(u64 address) in fpdt_address_valid() argument
[all …]
/linux-6.14.4/arch/arm/boot/dts/microchip/
Dat91-sama7g5ek.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * at91-sama7g5ek.dts - Device Tree file for SAMA7G5-EK board
11 /dts-v1/;
12 #include "sama7g5-pinfunc.h"
14 #include <dt-bindings/mfd/atmel-flexcom.h>
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/pinctrl/at91.h>
17 #include <dt-bindings/sound/microchip,pdmc.h>
20 model = "Microchip SAMA7G5-EK";
25 stdout-path = "serial0:115200n8";
[all …]
Dat91-sama5d27_wlsom1.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * at91-sama5d27_wlsom1.dtsi - Device Tree file for SAMA5D27 WLSOM1
11 #include "sama5d2-pinfunc.h"
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/mfd/atmel-flexcom.h>
14 #include <dt-bindings/pinctrl/at91.h>
18 compatible = "microchip,sama5d27-wlsom1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5";
26 clock-frequency = <32768>;
30 clock-frequency = <24000000>;
34 reg_5v: regulator-5v {
[all …]
/linux-6.14.4/include/linux/mtd/
Dpfow.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 /* Address of symbol "P" */
13 /* Address of symbol "F" */
15 /* Address of symbol "O" */
17 /* Address of symbol "W" */
22 /* Address in PFOW where prog buffer can be found */
26 /* Address command code register */
30 /* command address register lower address bits */
32 /* command address register upper address bits */
34 /* number of bytes to be proggrammed lower address bits */
[all …]
/linux-6.14.4/arch/arm/boot/dts/samsung/
Ds5pv210-aries.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
32 reserved-memory {
33 #address-cells = <1>;
34 #size-cells = <1>;
38 compatible = "shared-dma-pool";
39 no-map;
44 compatible = "shared-dma-pool";
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/usb/
Dfsl,imx8mp-dwc3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/fsl,imx8mp-dwc3.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Li Jun <[email protected]>
16 - items:
17 - const: fsl,imx95-dwc3
18 - const: fsl,imx8mp-dwc3
19 - const: fsl,imx8mp-dwc3
23 - description: Address and length of the register set for HSIO Block Control
[all …]
Dhisilicon,hi3798mv200-dwc3.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/hisilicon,hi3798mv200-dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yang Xiwen <[email protected]>
14 const: hisilicon,hi3798mv200-dwc3
16 '#address-cells':
19 '#size-cells':
26 - description: Controller bus clock
27 - description: Controller suspend clock
[all …]
/linux-6.14.4/drivers/pinctrl/samsung/
Dpinctrl-samsung.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
25 * enum pincfg_type - possible pin configuration types supported.
46 * packed together into a 16-bits. The upper 8-bits represent the configuration
47 * type and the lower 8-bits hold the value of the configuration type.
70 * enum pud_index - Possible index values to access the pud_val array.
84 * enum eint_type - possible external interrupt types.
104 /* maximum length of a pin in pin descriptor (example: "gpa0-0") */
135 * struct samsung_pin_bank_data: represent a controller pin-bank (init data).
137 * @pctl_offset: starting offset of the pin-bank registers.
[all …]
/linux-6.14.4/include/linux/mfd/
Drohm-generic.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
37 * struct rohm_dvs_config - dynamic voltage scaling register descriptions
39 * @level_map: bitmap representing supported run-levels for this
41 * @run_reg: register address for regulator config at 'run' state
44 * @idle_reg: register address for regulator config at 'idle' state
47 * @suspend_reg: register address for regulator config at 'suspend' state
48 * @suspend_mask: value mask for regulator voltages at 'suspend' state
49 * @suspend_on_mask: enable mask for regulator at 'suspend' state
50 * @lpsr_reg: register address for regulator config at 'lpsr' state
/linux-6.14.4/Documentation/arch/arm/samsung/
Dbootloader-interface.rst14 In the document "boot loader" means any of following: U-boot, proprietary
19 1. Non-Secure mode
21 Address: sysram_ns_base_addr
26 0x08 exynos_cpu_resume_ns, mcpm_entry_point System suspend
27 0x0c 0x00000bad (Magic cookie) System suspend
33 0x28 0x0 or last value during resume (Exynos542x) System suspend
39 Address: sysram_base_addr
51 Address: pmu_base_addr
56 0x0800 exynos_cpu_resume AFTR, suspend
57 0x0800 mcpm_entry_point (Exynos542x with MCPM) AFTR, suspend
[all …]
/linux-6.14.4/drivers/remoteproc/
Domap_remoteproc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2020 Texas Instruments Incorporated - http://www.ti.com/
8 * Ohad Ben-Cohen <[email protected]>
12 * Suman Anna <s-[email protected]>
13 * Hari Kanigeri <h-[email protected]>
27 #include <linux/dma-mapping.h>
31 #include <linux/omap-iommu.h>
32 #include <linux/omap-mailbox.h>
36 #include <clocksource/timer-ti-dm.h>
38 #include <linux/platform_data/dmtimer-omap.h>
[all …]
/linux-6.14.4/drivers/net/ethernet/i825xx/
Dsun3_82586.h1 /* SPDX-License-Identifier: GPL-2.0-only */
8 * copyrights (c) 1994 by Michael Hipp ([email protected]-tuebingen.de)
11 * crynwr-packet-driver by Russ Nelson
12 * Garret A. Wollman's i82586-driver for BSD
53 char *iscp; /* pointer to the iscp-block */
65 char *scb_base; /* base-address of all 16-bit offsets */
79 unsigned short crc_errs; /* CRC-Error counter */
89 #define RUC_NOP 0x0000 /* NOP-command */
91 #define RUC_RESUME 0x0020 /* resume RU after suspend */
92 #define RUC_SUSPEND 0x0030 /* suspend RU */
[all …]
/linux-6.14.4/arch/arm/boot/dts/rockchip/
Drv1126-edgeble-neu2.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 compatible = "edgeble,neural-compute-module-2", "rockchip,rv1126";
14 vccio_flash: regulator-vccio-flash {
15 compatible = "regulator-fixed";
16 enable-active-high;
18 pinctrl-names = "default";
19 pinctrl-0 = <&flash_vol_sel>;
20 regulator-name = "vccio_flash";
21 regulator-always-on;
22 regulator-boot-on;
[all …]
Drk3288-phycore-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device tree file for Phytec phyCORE-RK3288 SoM
8 #include <dt-bindings/net/ti-dp83867.h>
13 compatible = "phytec,rk3288-phycore-som", "rockchip,rk3288";
29 ext_gmac: external-gmac-clock {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <125000000>;
33 clock-output-names = "ext_gmac";
36 leds: user-leds {
[all …]
/linux-6.14.4/arch/arm64/boot/dts/rockchip/
Dpx30-ringneck.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/leds/common.h>
20 attiny-updi-gate-regulator {
21 compatible = "regulator-output";
22 vout-supply = <&vg_attiny_updi>;
25 emmc_pwrseq: emmc-pwrseq {
26 compatible = "mmc-pwrseq-emmc";
27 pinctrl-0 = <&emmc_reset>;
28 pinctrl-names = "default";
[all …]
Drk3328-orangepi-r1-plus.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Based on rk3328-nanopi-r2s.dts, which is:
4 * Copyright (c) 2020 David Bauer <mail@david-bauer.net>
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/leds/common.h>
21 stdout-path = "serial2:1500000n8";
24 gmac_clk: gmac-clock {
25 compatible = "fixed-clock";
26 clock-frequency = <125000000>;
[all …]
Drk3588s-gameforce-ace.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/linux-event-codes.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/pwm/pwm.h>
10 #include <dt-bindings/thermal/thermal.h>
11 #include <dt-bindings/usb/pd.h>
16 chassis-type = "handset";
[all …]
Drk3399-eaidk-610.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/pwm/pwm.h>
9 #include <dt-bindings/usb/pd.h>
13 model = "OPEN AI LAB EAIDK-610";
14 compatible = "openailab,eaidk-610", "rockchip,rk3399";
24 compatible = "pwm-backlight";
26 brightness-levels = <
59 default-brightness-level = <200>;
[all …]
/linux-6.14.4/arch/arm/mach-mvebu/
Dpm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Suspend/resume support. Currently supporting Armada XP only.
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
17 #include <linux/suspend.h>
20 #include <asm/suspend.h>
61 /* Prepare to go to self-refresh */ in mvebu_pm_powerdown()
78 * base, which is why we hardcode the 0xd0000000 base address, the one
92 np = of_find_node_by_name(NULL, "internal-regs"); in mvebu_internal_reg_base()
96 * Ask the DT what is the internal register address on this in mvebu_internal_reg_base()
97 * platform. In the mvebu-mbus DT binding, 0xf0010000 in mvebu_internal_reg_base()
[all …]
/linux-6.14.4/drivers/net/ipa/
Dgsi.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2018-2024 Linaro Ltd.
31 void *virt; /* ring array base address */
51 * but taken from a fixed-size pool. The number of elements required for
63 void *base; /* base address of element pool */
68 dma_addr_t addr; /* DMA address if DMA pool (or 0) */
81 struct gsi_trans **map; /* TRE -> transaction map */
94 GSI_CHANNEL_STATE_FLOW_CONTROLLED = 0x5, /* IPA v4.2-v4.9 */
158 * gsi_setup() - Set up the GSI subsystem
[all …]
/linux-6.14.4/arch/arm64/boot/dts/freescale/
Dimx8mm-phycore-som.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/net/ti-dp83867.h>
11 model = "PHYTEC phyCORE-i.MX8MM";
12 compatible = "phytec,imx8mm-phycore-som", "fsl,imx8mm";
24 reg_vdd_3v3_s: regulator-vdd-3v3-s {
25 compatible = "regulator-fixed";
26 regulator-always-on;
27 regulator-boot-on;
28 regulator-max-microvolt = <3300000>;
29 regulator-min-microvolt = <3300000>;
[all …]
/linux-6.14.4/arch/arm/include/asm/
Dfirmware.h1 /* SPDX-License-Identifier: GPL-2.0-only */
30 * Sets boot address of specified physical CPU
34 * Gets boot address of specified physical CPU
46 * Enter system-wide suspend.
48 int (*suspend)(void); member
50 * Restore state of privileged hardware after system-wide suspend.
62 * otherwise returns -ENOSYS
65 ((firmware_ops->op) ? firmware_ops->op(__VA_ARGS__) : (-ENOSYS))
/linux-6.14.4/drivers/net/wwan/iosm/
Diosm_ipc_pcie.h1 /* SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020-21 Intel Corporation.
35 * enum ipc_pcie_sleep_state - Enum type to different sleep state transitions
45 * struct iosm_pcie - IPC_PCIE struct.
46 * @pci: Address of the device description
48 * @ipc_regs: Remapped CP doorbell address of the irq register
50 * @scratchpad: Remapped CP scratchpad address, to send the
61 * @suspend: S2IDLE sleep/active
76 unsigned long suspend; member
81 * struct ipc_skb_cb - Struct definition of the socket buffer which is mapped to
[all …]
/linux-6.14.4/drivers/net/wireless/ath/ath11k/
Dhif.h1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
13 u32 (*read32)(struct ath11k_base *ab, u32 address);
14 void (*write32)(struct ath11k_base *ab, u32 address, u32 data);
22 int (*suspend)(struct ath11k_base *ab); member
38 if (ab->hif.ops->ce_irq_enable) in ath11k_hif_ce_irq_enable()
39 ab->hif.ops->ce_irq_enable(ab); in ath11k_hif_ce_irq_enable()
44 if (ab->hif.ops->ce_irq_disable) in ath11k_hif_ce_irq_disable()
45 ab->hif.ops->ce_irq_disable(ab); in ath11k_hif_ce_irq_disable()
[all …]

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