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/linux-6.14.4/Documentation/devicetree/bindings/clock/
Dti,cdce925.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexander Stein <[email protected]-group.com>
15 - CDCE(L)913: 1-PLL, 3 Outputs https://www.ti.com/product/cdce913
16 - CDCE(L)925: 2-PLL, 5 Outputs https://www.ti.com/product/cdce925
17 - CDCE(L)937: 3-PLL, 7 Outputs https://www.ti.com/product/cdce937
18 - CDCE(L)949: 4-PLL, 9 Outputs https://www.ti.com/product/cdce949
23 - ti,cdce913
24 - ti,cdce925
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Dmediatek,mt8186-fhctl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8186-fhctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek frequency hopping and spread spectrum clocking control
10 - Edward-JW Yang <edward-[email protected]>
15 Spread spectrum clocking (SSC) is another function provided by this hardware.
20 - mediatek,mt6795-fhctl
21 - mediatek,mt8173-fhctl
22 - mediatek,mt8186-fhctl
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Drenesas,9series.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas 9-series I2C PCIe clock generators
10 The Renesas 9-series are I2C PCIe clock generators providing
16 - 9FGV0241:
17 0 -- DIF0
18 1 -- DIF1
19 - 9FGV0441:
20 0 -- DIF0
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Dnuvoton,ma35d1-clk.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/nuvoton,ma35d1-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chi-Fang Li <[email protected]>
11 - Jacky Huang <[email protected]>
18 include/dt-bindings/clock/ma35d1-clk.h
23 - const: nuvoton,ma35d1-clk
28 "#clock-cells":
34 nuvoton,pll-mode:
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/linux-6.14.4/Documentation/devicetree/bindings/clock/ti/
Ddpll.txt4 register-mapped DPLL with usually two selectable input clocks
9 sub-types, which effectively result in slightly different setup
12 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
15 - compatible : shall be one of:
16 "ti,omap3-dpll-clock",
17 "ti,omap3-dpll-core-clock",
18 "ti,omap3-dpll-per-clock",
19 "ti,omap3-dpll-per-j-type-clock",
20 "ti,omap4-dpll-clock",
21 "ti,omap4-dpll-x2-clock",
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/linux-6.14.4/Documentation/ABI/testing/
Dsysfs-platform-dptf4 Contact: linux-[email protected]
6 (RO) The charger type - Traditional, Hybrid or NVDC.
11 Contact: linux-[email protected]
19 Contact: linux-[email protected]
27 Contact: linux-[email protected]
33 - 0x00 = DC
34 - 0x01 = AC
35 - 0x02 = USB
36 - 0x03 = Wireless Charger
43 Contact: linux-[email protected]
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/linux-6.14.4/Documentation/driver-api/thermal/
Dintel_dptf.rst1 .. SPDX-License-Identifier: GPL-2.0
12 ------------
31 ----------------------------
43 "42A441D6-AE6A-462b-A84B-4A8CE79027D3" : Passive 1
45 "3A95C389-E4B8-4629-A526-C52C88626BAE" : Active
47 "97C68AE7-15FA-499c-B8C9-5DA81D606E0A" : Critical
49 "63BE270F-1C11-48FD-A6F7-3AF253FF3E2D" : Adaptive performance
51 "5349962F-71E6-431D-9AE8-0A635B710AEE" : Emergency call
53 "9E04115A-AE87-4D1C-9500-0F3E340BFE75" : Passive 2
55 "F5A35014-C209-46A4-993A-EB56DE7530A1" : Power Boss
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/linux-6.14.4/Documentation/devicetree/bindings/ata/
Dimx-sata.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/imx-sata.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <[email protected]>
19 - fsl,imx53-ahci
20 - fsl,imx6q-ahci
21 - fsl,imx6qp-ahci
22 - fsl,imx8qm-ahci
33 - description: sata clock
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/linux-6.14.4/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
Dsmu11_driver_if_sienna_cichlid.h53 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
54 #define MAX_SMNCLK_DPM_LEVEL (NUM_SMNCLK_DPM_LEVELS - 1)
55 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
56 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
57 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1)
58 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1)
59 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
60 #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
61 #define MAX_PIXCLK_DPM_LEVEL (NUM_PIXCLK_DPM_LEVELS - 1)
62 #define MAX_PHYCLK_DPM_LEVEL (NUM_PHYCLK_DPM_LEVELS - 1)
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Dsmu11_driver_if_arcturus.h44 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
45 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1)
46 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1)
47 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
48 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
49 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
50 #define MAX_FCLK_DPM_LEVEL (NUM_FCLK_DPM_LEVELS - 1)
51 #define MAX_XGMI_LEVEL (NUM_XGMI_LEVELS - 1)
52 #define MAX_XGMI_PSTATE_LEVEL (NUM_XGMI_PSTATE_LEVELS - 1)
457 uint8_t VoltageMode; // 0 - AVFS only, 1- min(AVFS,SS), 2-SS only
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/linux-6.14.4/drivers/clk/
Dclk-renesas-pcie.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for Renesas 9-series PCIe clock generator driver
6 * - 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ
8 * - 9FGV0241
9 * - 9FGV0441
10 * - 9FGV0841
15 #include <linux/clk-provider.h>
56 /* Structure to describe features of a particular 9-series model */
74 * Renesas 9-series i2c regmap
110 return -EIO; in rs9_regmap_i2c_write()
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/linux-6.14.4/Documentation/misc-devices/
Dics932s401.rst18 -----------
22 This chip has 4 clock outputs--a base clock for the CPU (which is likely
25 frequency. If spread spectrum mode is enabled, the driver also reports by what
26 percent the clock signal is being spread, which should be between 0 and -0.5%.
33 ----------------
/linux-6.14.4/drivers/gpu/drm/nouveau/dispnv04/
Ddfp.c5 * Copyright 2007-2009 Stuart Bennett
58 * this does not give a correct answer for off-chip dvi, but there's no in nv04_dfp_get_bound_head()
61 int ramdac = (dcbent->or & DCB_OUTPUT_C) >> 2; in nv04_dfp_get_bound_head()
72 * Luckily we do know the values ;-) in nv04_dfp_bind_head()
78 int ramdac = (dcbent->or & DCB_OUTPUT_C) >> 2; in nv04_dfp_bind_head()
84 if (dcbent->type == DCB_OUTPUT_LVDS) in nv04_dfp_bind_head()
87 nv_write_tmds(dev, dcbent->or, 0, 0x04, tmds04); in nv04_dfp_bind_head()
90 nv_write_tmds(dev, dcbent->or, 1, 0x04, tmds04 ^ 0x08); in nv04_dfp_bind_head()
95 struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg; in nv04_dfp_disable()
115 struct drm_device *dev = encoder->dev; in nv04_dfp_update_fp_control()
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/linux-6.14.4/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/
Ddce120_clk_mgr.c2 * Copyright 2012-16 Advanced Micro Devices, Inc.
36 /*ClocksStateInvalid - should not be used*/
38 /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
48 * dce121_clock_patch_xgmi_ss_info() - Save XGMI spread spectrum info
51 * Reads from VBIOS the XGMI spread spectrum info and saves it within
54 * sets the ->xgmi_enabled flag.
60 struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios; in dce121_clock_patch_xgmi_ss_info()
62 clk_mgr_dce->xgmi_enabled = false; in dce121_clock_patch_xgmi_ss_info()
64 result = bp->funcs->get_spread_spectrum_info(bp, AS_SIGNAL_TYPE_XGMI, in dce121_clock_patch_xgmi_ss_info()
67 clk_mgr_dce->xgmi_enabled = true; in dce121_clock_patch_xgmi_ss_info()
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/linux-6.14.4/drivers/phy/starfive/
Dphy-jh7110-pcie.c1 // SPDX-License-Identifier: GPL-2.0+
49 if (!data->stg_syscon || !data->sys_syscon) { in phy_usb3_mode_set()
50 dev_err(&data->phy->dev, "doesn't support usb3 mode\n"); in phy_usb3_mode_set()
51 return -EINVAL; in phy_usb3_mode_set()
54 regmap_update_bits(data->stg_syscon, data->stg_pcie_mode, in phy_usb3_mode_set()
56 regmap_update_bits(data->stg_syscon, data->stg_pcie_usb, in phy_usb3_mode_set()
58 regmap_update_bits(data->stg_syscon, data->stg_pcie_usb, in phy_usb3_mode_set()
62 regmap_update_bits(data->sys_syscon, data->sys_phy_connect, in phy_usb3_mode_set()
65 /* Configuare spread-spectrum mode: down-spread-spectrum */ in phy_usb3_mode_set()
66 writel(PCIE_USB3_PHY_ENABLE, data->regs + PCIE_USB3_PHY_PLL_CTL_OFF); in phy_usb3_mode_set()
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/linux-6.14.4/drivers/phy/rockchip/
Dphy-rockchip-naneng-combphy.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/phy/phy.h>
171 temp = readl(priv->mmio + reg); in rockchip_combphy_updatel()
173 writel(temp, priv->mmio + reg); in rockchip_combphy_updatel()
181 tmp = en ? reg->enable : reg->disable; in rockchip_combphy_param_write()
182 mask = GENMASK(reg->bitend, reg->bitstart); in rockchip_combphy_param_write()
183 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); in rockchip_combphy_param_write()
185 return regmap_write(base, reg->offset, val); in rockchip_combphy_param_write()
190 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rockchip_combphy_is_ready()
193 mask = GENMASK(cfg->pipe_phy_status.bitend, in rockchip_combphy_is_ready()
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/linux-6.14.4/drivers/scsi/isci/
Dprobe_roms.h7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
103 * - A value of 1 indicates generation 1 (i.e. 1.5 Gb/s).
104 * - A value of 2 indicates generation 2 (i.e. 3.0 Gb/s).
105 * - A value of 3 indicates generation 3 (i.e. 6.0 Gb/s).
228 * Spread Spectrum Clocking (SSC) settings for SATA and SAS.
234 * NOTE: Max spread for SATA is +0 / -5000 PPM.
235 * Down-spreading SSC (only method allowed for SATA):
237 * SATA SSC Tx at +0 / -1419 PPM Spread = 0x2
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/linux-6.14.4/include/linux/phy/
Dphy-dp.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 * struct phy_configure_opts_dp - DisplayPort PHY configuration set
54 * Pre-emphasis levels, as specified by DisplayPort specification, to be
64 * Flag indicating, whether or not to enable spread-spectrum clocking.
91 * and pre-emphasis to requested values. Only lanes specified
/linux-6.14.4/Documentation/gpu/amdgpu/
Damdgpu-glossary.rst7 'Documentation/gpu/amdgpu/display/dc-glossary.rst'.
90 Multi-Media HUB
96 PowerPlay Library - PowerPlay is the power management component.
117 Spread Spectrum
/linux-6.14.4/arch/arm/boot/dts/nxp/imx/
Dimx6q-cubox-i.dts4 * This file is dual-licensed: you can use it either under the terms
41 /dts-v1/;
44 #include "imx6qdl-sr-som.dtsi"
45 #include "imx6qdl-sr-som-brcm.dtsi"
46 #include "imx6qdl-cubox-i.dtsi"
49 model = "SolidRun Cubox-i Dual/Quad";
50 compatible = "solidrun,cubox-i/q", "fsl,imx6q";
55 fsl,transmit-level-mV = <1104>;
56 fsl,transmit-boost-mdB = <0>;
57 fsl,transmit-atten-16ths = <9>;
[all …]
Dimx6q-cubox-i-som-v15.dts4 * This file is dual-licensed: you can use it either under the terms
41 /dts-v1/;
44 #include "imx6qdl-sr-som.dtsi"
45 #include "imx6qdl-sr-som-ti.dtsi"
46 #include "imx6qdl-cubox-i.dtsi"
49 model = "SolidRun Cubox-i Dual/Quad (1.5som)";
50 compatible = "solidrun,cubox-i/q", "fsl,imx6q";
55 fsl,transmit-level-mV = <1104>;
56 fsl,transmit-boost-mdB = <0>;
57 fsl,transmit-atten-16ths = <9>;
[all …]
Dimx6q-cubox-i-emmc-som-v15.dts4 * This file is dual-licensed: you can use it either under the terms
41 /dts-v1/;
44 #include "imx6qdl-sr-som.dtsi"
45 #include "imx6qdl-sr-som-ti.dtsi"
46 #include "imx6qdl-sr-som-emmc.dtsi"
47 #include "imx6qdl-cubox-i.dtsi"
50 model = "SolidRun Cubox-i Dual/Quad (1.5som+emmc)";
51 compatible = "solidrun,cubox-i/q", "fsl,imx6q";
56 fsl,transmit-level-mV = <1104>;
57 fsl,transmit-boost-mdB = <0>;
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/linux-6.14.4/drivers/gpu/drm/amd/display/include/
Dddc_service_types.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
103 /* support for Spread Spectrum(SS) */
105 /* DP link settings (laneCount, linkRate, Spread) */
111 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
/linux-6.14.4/Documentation/devicetree/bindings/phy/
Drenesas,usb3-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,usb3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car generation 3 USB 3.0 PHY
10 - Yoshihiro Shimoda <[email protected]>
15 - enum:
16 - renesas,r8a774a1-usb3-phy # RZ/G2M
17 - renesas,r8a774b1-usb3-phy # RZ/G2N
18 - renesas,r8a774e1-usb3-phy # RZ/G2H
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/linux-6.14.4/Documentation/devicetree/bindings/regulator/
Drenesas,raa215300.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biju Das <[email protected]>
13 The RAA215300 is a high-performance, low-cost 9-channel PMIC designed for
14 32-bit and 64-bit MCU and MPU applications. It supports DDR3, DDR3L, DDR4,
16 built-in Real-Time Clock (RTC), 32kHz crystal oscillator, and coin cell
18 ideal for System-On-Module (SOM) applications. A spread spectrum feature
19 provides an ease-of-use solution for noise-sensitive audio or RF applications.
25 …-power-management/multi-channel-power-management-ics-pmics/ssdsoc-power-management-ics-pmic-and-pm…
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