| /linux-6.14.4/arch/arm64/boot/dts/arm/ |
| D | foundation-v8-spin-table.dtsi | 4 * ARMv8 Foundation model DTS (spin table configuration)
8 enable-method = "spin-table";
9 cpu-release-addr = <0x0 0x8000fff8>;
13 enable-method = "spin-table";
14 cpu-release-addr = <0x0 0x8000fff8>;
18 enable-method = "spin-table";
19 cpu-release-addr = <0x0 0x8000fff8>;
23 enable-method = "spin-table";
24 cpu-release-addr = <0x0 0x8000fff8>;
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| D | rtsm_ve-aemv8a.dts | 1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
22 interrupt-parent = <&gic>;
23 #address-cells = <2>;
24 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
38 #address-cells = <2>;
[all …]
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| /linux-6.14.4/Documentation/devicetree/bindings/arm/ |
| D | cpus.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <[email protected]>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
71 * If cpus node's #address-cells property is set to 2
79 * If cpus node's #address-cells property is set to 1
[all …]
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| /linux-6.14.4/drivers/gpu/drm/i915/gt/ |
| D | selftest_mocs.c | 1 // SPDX-License-Identifier: MIT
17 struct drm_i915_mocs_table table; member
33 ce->ring_size = SZ_16K; in mocs_context_create()
43 err = -ETIME; in request_add_sync()
49 static int request_add_spin(struct i915_request *rq, struct igt_spinner *spin) in request_add_spin() argument
55 if (spin && !igt_wait_for_spinner(spin, rq)) in request_add_spin()
56 err = -ETIME; in request_add_spin()
69 flags = get_mocs_settings(gt->i915, &arg->table); in live_mocs_init()
71 return -EINVAL; in live_mocs_init()
74 arg->l3cc = &arg->table; in live_mocs_init()
[all …]
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| /linux-6.14.4/Documentation/devicetree/bindings/cpu/ |
| D | cpu-topology.txt | 6 1 - Introduction
12 - socket
13 - cluster
14 - core
15 - thread
18 symmetric multi-threading (SMT) is supported or not.
29 Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be
39 2 - cpu-map node
42 The ARM/RISC-V CPU topology is defined within the cpu-map node, which is a direct
46 - cpu-map node
[all …]
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| /linux-6.14.4/arch/arm64/boot/dts/apple/ |
| D | t6002.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
15 #include "multi-die-cpp.h"
17 #include "t600x-common.dtsi"
20 compatible = "apple,t6002", "apple,arm-platform";
22 #address-cells = <2>;
23 #size-cells = <2>;
[all …]
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| D | t600x-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
18 cpu-map {
63 enable-method = "spin-table";
64 cpu-release-addr = <0 0>; /* To be filled by loader */
65 next-level-cache = <&l2_cache_0>;
66 i-cache-size = <0x20000>;
[all …]
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| D | t8015.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
16 interrupt-parent = <&aic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
20 clkref: clock-ref {
21 compatible = "fixed-clock";
[all …]
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| D | t7001.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/apple-aic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/pinctrl/apple.h>
15 interrupt-parent = <&aic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
23 clkref: clock-ref {
24 compatible = "fixed-clock";
[all …]
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| D | t8011.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
16 interrupt-parent = <&aic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
20 clkref: clock-ref {
21 compatible = "fixed-clock";
[all …]
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| D | t8103.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
16 compatible = "apple,t8103", "apple,arm-platform";
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <2>;
23 #size-cells = <0>;
[all …]
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| D | t8112.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
14 #include <dt-bindings/spmi/spmi.h>
17 compatible = "apple,t8112", "apple,arm-platform";
19 #address-cells = <2>;
20 #size-cells = <2>;
23 #address-cells = <2>;
[all …]
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| /linux-6.14.4/arch/arm64/boot/dts/qcom/ |
| D | msm8992-lg-h815.dts | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 /dts-v1/;
13 #include <dt-bindings/leds/common.h>
16 /delete-node/ &cont_splash_mem;
19 /delete-node/ &dfps_data_mem;
24 chassis-type = "handset";
26 qcom,msm-id = <0xfb 0x0>;
27 qcom,pmic-id = <0x10009 0x1000a 0x0 0x0>;
28 qcom,board-id = <0xb64 0x0>;
31 /delete-node/ psci;
[all …]
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| /linux-6.14.4/arch/arm64/boot/dts/altera/ |
| D | socfpga_stratix10_swvp.dts | 1 // SPDX-License-Identifier: GPL-2.0
10 compatible = "altr,socfpga-stratix10-swvp", "altr,socfpga-stratix10";
27 stdout-path = "serial1:115200n8";
28 linux,initrd-start = <0x10000000>;
29 linux,initrd-end = <0x125c8324>;
39 enable-method = "spin-table";
40 cpu-release-addr = <0x0 0x0000fff8>;
44 enable-method = "spin-table";
45 cpu-release-addr = <0x0 0x0000fff8>;
49 enable-method = "spin-table";
[all …]
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| /linux-6.14.4/arch/arm64/boot/dts/freescale/ |
| D | s32v234.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2015-2016 Freescale Semiconductor, Inc.
4 * Copyright 2016-2018 NXP
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
23 #address-cells = <2>;
24 #size-cells = <0>;
28 compatible = "arm,cortex-a53";
[all …]
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| /linux-6.14.4/arch/arm64/boot/dts/microchip/ |
| D | sparx5_pcb_common.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
14 enable-method = "spin-table";
18 enable-method = "spin-table";
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| /linux-6.14.4/arch/arm/boot/dts/broadcom/ |
| D | bcm2837.dtsi | 2 #include "bcm2835-common.dtsi"
10 dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
12 local_intc: interrupt-controller@40000000 {
13 compatible = "brcm,bcm2836-l1-intc";
15 interrupt-controller;
16 #interrupt-cells = <2>;
17 interrupt-parent = <&local_intc>;
21 arm-pmu {
22 compatible = "arm,cortex-a53-pmu";
23 interrupt-parent = <&local_intc>;
[all …]
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| /linux-6.14.4/arch/arm64/boot/dts/toshiba/ |
| D | tmpv7708.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * (C) Copyright 2018 - 2020, Toshiba Corporation.
10 #include <dt-bindings/clock/toshiba,tmpv770x.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 /memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
23 #size-cells = <0>;
[all …]
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| /linux-6.14.4/drivers/clk/stm32/ |
| D | clk-stm32-core.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
7 #include <linux/clk-provider.h>
16 u32 *table; member
32 const struct clk_div_table *table; member
95 spinlock_t *lock; /* spin lock */
105 spinlock_t *lock; /* spin lock */
115 spinlock_t *lock; /* spin lock */
127 spinlock_t *lock; /* spin lock */
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| /linux-6.14.4/arch/powerpc/platforms/85xx/ |
| D | smp.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright 2006-2008, 2011-2012, 2015 Freescale Semiconductor Inc.
26 #include <asm/text-patching.h>
58 qoriq_pm_ops->freeze_time_base(true); in mpc85xx_give_timebase()
61 * e5500/e6500 have a workaround for erratum A-006958 in place in mpc85xx_give_timebase()
62 * that will reread the timebase until TBL is non-zero. in mpc85xx_give_timebase()
66 * TBL is non-zero, we ensure that TB does not change. We don't in mpc85xx_give_timebase()
91 qoriq_pm_ops->freeze_time_base(false); in mpc85xx_give_timebase()
122 qoriq_pm_ops->irq_mask(cpu); in smp_85xx_cpu_offline_self()
131 cur_cpu_spec->cpu_down_flush(); in smp_85xx_cpu_offline_self()
[all …]
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| /linux-6.14.4/Documentation/hwmon/ |
| D | lm93.rst | 10 Addresses scanned: I2C 0x2c-0x2e
18 Addresses scanned: I2C 0x2c-0x2e
24 - Mark M. Hoffman <[email protected]>
25 - Ported to 2.6 by Eric J. Bowersox <[email protected]>
26 - Adapted to 2.6.20 by Carsten Emde <[email protected]>
27 - Modified for mainline integration by Hans J. Koch <[email protected]>
30 -----------------
33 Set to non-zero to force some initializations (default is 0).
38 Configures in7 and in8 limit type, where 0 means absolute and non-zero
54 --------------------
[all …]
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| /linux-6.14.4/arch/powerpc/boot/dts/ |
| D | iss4xx-mpic.dts | 15 /dts-v1/;
20 #address-cells = <2>;
21 #size-cells = <1>;
22 model = "ibm,iss-4xx";
23 compatible = "ibm,iss-4xx";
24 dcr-parent = <&{/cpus/cpu@0}>;
31 #address-cells = <1>;
32 #size-cells = <0>;
38 clock-frequency = <100000000>; // 100Mhz :-)
39 timebase-frequency = <100000000>;
[all …]
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| /linux-6.14.4/arch/arm64/kernel/ |
| D | smp_spin_table.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Spin Table SMP initialisation
50 return -ENODEV; in smp_spin_table_cpu_init()
55 ret = of_property_read_u64(dn, "cpu-release-addr", in smp_spin_table_cpu_init()
58 pr_err("CPU %d: missing or invalid cpu-release-addr property\n", in smp_spin_table_cpu_init()
72 return -ENODEV; in smp_spin_table_cpu_prepare()
75 * The cpu-release-addr may or may not be inside the linear mapping. in smp_spin_table_cpu_prepare()
83 return -ENOMEM; in smp_spin_table_cpu_prepare()
87 * endianness of the kernel. Therefore, any boot-loaders that in smp_spin_table_cpu_prepare()
89 * boot-loader's endianness before jumping. This is mandated by in smp_spin_table_cpu_prepare()
[all …]
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| /linux-6.14.4/arch/arm64/boot/dts/apm/ |
| D | apm-shadowcat.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC
9 compatible = "apm,xgene-shadowcat";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
22 enable-method = "spin-table";
23 cpu-release-addr = <0x1 0x0000fff8>;
[all …]
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| /linux-6.14.4/kernel/locking/ |
| D | qspinlock_paravirt.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
16 * pv_wait(u8 *ptr, u8 val) -- suspends the vcpu if *ptr == val
17 * pv_kick(cpu) -- wakes a suspended vcpu
31 * mitigates the slight slowdown for non-overcommitted guest with this
32 * aggressive wait-early mechanism.
64 * pv_wait_head_or_lock() to signal that it is ready to spin on the lock.
88 int val = atomic_read(&lock->val); in pv_hybrid_queued_unfair_trylock()
92 try_cmpxchg_acquire(&lock->locked, &old, _Q_LOCKED_VAL)) { in pv_hybrid_queued_unfair_trylock()
112 WRITE_ONCE(lock->pending, 1); in set_pending()
124 return !READ_ONCE(lock->locked) && in trylock_clear_pending()
[all …]
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