Home
last modified time | relevance | path

Searched +full:spare +full:- +full:regs (Results 1 – 25 of 58) sorted by relevance

123

/linux-6.14.4/drivers/mtd/nand/raw/
Dmpc5121_nfc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2004-2008 Freescale Semiconductor, Inc.
34 /* Addresses for NFC SPARE BUFFER areas */
110 void __iomem *regs; member
127 return in_be16(prv->regs + reg); in nfc_read()
136 out_be16(prv->regs + reg, val); in nfc_write()
207 wake_up(&prv->irq_waitq); in mpc5121_nfc_irq()
221 rv = wait_event_timeout(prv->irq_waitq, in mpc5121_nfc_done()
225 dev_warn(prv->dev, in mpc5121_nfc_done()
236 u32 pagemask = chip->pagemask; in mpc5121_nfc_addr_cycle()
[all …]
Dmtk_nand.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 * Jorge Ramirez-Ortiz <jorge.ramirez-[email protected]>
10 #include <linux/dma-mapping.h>
19 #include <linux/mtd/nand-ecc-mtk.h>
89 #define MTK_NAME "mtk-nand"
150 void __iomem *regs; member
161 * supported spare size of each IP.
162 * order should be the same with the spare size bitfiled defination of
185 return (u8 *)p + i * chip->ecc.size; in data_ptr()
197 if (i < mtk_nand->bad_mark.sec) in oob_ptr()
[all …]
Dmarvell_nand.c1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
23 * bytes (also called "spare" bytes in the driver). This engine
28 * +-------------------------------------------------------------+
30 * +-------------------------------------------------------------+
39 * +-----------------------------------------
41 * +-----------------------------------------
43 * -------------------------------------------
45 * -------------------------------------------
[all …]
Dqcom_nandc.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
18 #include <linux/mtd/nand-qpic-common.h>
23 * @page_offset: offset of the partition where spare data is not protected
25 * @page_offset: size of the partition where spare data is not protected
66 * @nr_boot_partitions: count of the boot partitions where spare data is not
71 * of a page, consisting of all data, ecc, spare
82 * ecc/non-ecc mode for the current nand flash
132 ((u8 *)chip->controller - sizeof(struct qcom_nand_controller)); in get_qcom_nand_controller()
137 return ioread32(nandc->base + offset); in nandc_read()
[all …]
Dmxc_nand.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
28 #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
29 #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
30 #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
31 #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
32 #define NFC_V1_V2_CONFIG (host->regs + 0x0a)
33 #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
34 #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
35 #define NFC_V21_RSLTSPARE_AREA (host->regs + 0x10)
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/remoteproc/
Dqcom,sc7180-mss-pil.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sc7180-mss-pil.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sibi Sankar <[email protected]>
19 - qcom,sc7180-mss-pil
23 - description: MSS QDSP6 registers
24 - description: RMB registers
26 reg-names:
28 - const: qdsp6
[all …]
/linux-6.14.4/arch/x86/virt/vmx/tdx/
Dtdxcall.S1 /* SPDX-License-Identifier: GPL-2.0 */
2 #include <asm/asm-offsets.h>
14 * TDX_MODULE_CALL - common helper macro for both
17 * TDCALL - used by TDX guests to make requests to the
19 * SEAMCALL - used by TDX hosts to make requests to the
22 *-------------------------------------------------------------------------
24 *-------------------------------------------------------------------------
27 * RAX - TDCALL/SEAMCALL Leaf number.
28 * RCX,RDX,RDI,RSI,RBX,R8-R15 - TDCALL/SEAMCALL Leaf specific input registers.
32 * RAX - TDCALL/SEAMCALL instruction error code.
[all …]
/linux-6.14.4/drivers/gpu/drm/xe/
Dxe_guc_db_mgr.c1 // SPDX-License-Identifier: MIT
11 #include "regs/xe_guc_regs.h"
26 * In SR-IOV mode, the doorbells are treated as shared resource and PF must
47 #define dbm_mutex(_dbm) (&dbm_to_guc(_dbm)->submission_state.lock)
58 weight = bitmap_weight(dbm->bitmap, dbm->count); in __fini_dbm()
63 weight, dbm->count); in __fini_dbm()
67 bitmap_free(dbm->bitmap); in __fini_dbm()
68 dbm->bitmap = NULL; in __fini_dbm()
69 dbm->count = 0; in __fini_dbm()
75 * xe_guc_db_mgr_init() - Initialize GuC Doorbells Manager.
[all …]
Dxe_ggtt.c1 // SPDX-License-Identifier: MIT
8 #include <linux/fault-inject.h>
9 #include <linux/io-64-nonatomic-lo-hi.h>
17 #include "regs/xe_gt_regs.h"
18 #include "regs/xe_gtt_defs.h"
19 #include "regs/xe_regs.h"
38 * for resources that are accessible to privileged (i.e. kernel-mode) processes,
39 * and not tied to a specific user-level process. For example, the Graphics
40 * micro-Controller (GuC) and Display Engine (if present) utilize this Global
44 * address that can be accessed by HW. The GGTT is a flat, single-level table.
[all …]
Dxe_gt_sriov_pf_config.c1 // SPDX-License-Identifier: MIT
3 * Copyright © 2023-2024 Intel Corporation
12 #include "regs/xe_guc_regs.h"
54 return xe_guc_ct_send_block(&guc->ct, request, ARRAY_SIZE(request)); in guc_action_update_vf_cfg()
62 struct xe_guc *guc = &gt->uc.guc; in pf_send_vf_cfg_reset()
67 return ret <= 0 ? ret : -EPROTO; in pf_send_vf_cfg_reset()
79 struct xe_guc *guc = &gt->uc.guc; in pf_send_vf_cfg_klvs()
92 xe_map_memcpy_to(xe, &bo->vmap, 0, klvs, bytes); in pf_send_vf_cfg_klvs()
102 * Return: 0 on success, -ENOKEY if some KLVs were not updated, -EPROTO if reply was malformed,
115 int err = ret < 0 ? ret : ret < num_klvs ? -ENOKEY : -EPROTO; in pf_push_vf_cfg_klvs()
[all …]
/linux-6.14.4/drivers/mtd/nand/
Decc-mxic.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/dma-mapping.h>
19 #include <linux/mtd/nand-ecc-mxic.h>
57 /* Spare Data Size */
74 /* SDMA Address of Spare Data */
80 /* Status bytes between each chunk of spare data */
89 void __iomem *regs; member
126 struct nand_ecc_engine *eng = nand->ecc.engine; in nand_to_mxic()
128 if (eng->integration == NAND_ECC_ENGINE_INTEGRATION_EXTERNAL) in nand_to_mxic()
140 if (section < 0 || section >= ctx->steps) in mxic_ecc_ooblayout_ecc()
[all …]
Decc-mtk.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 * Jorge Ramirez-Ortiz <jorge.ramirez-[email protected]>
10 #include <linux/dma-mapping.h>
18 #include <linux/mtd/nand-ecc-mtk.h>
61 void __iomem *regs; member
129 struct device *dev = ecc->dev; in mtk_ecc_wait_idle()
133 ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val, in mtk_ecc_wait_idle()
146 dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]) in mtk_ecc_irq()
149 dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]); in mtk_ecc_irq()
150 if (dec & ecc->sectors) { in mtk_ecc_irq()
[all …]
/linux-6.14.4/drivers/soc/tegra/fuse/
Dfuse-tegra.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2023, NVIDIA CORPORATION. All rights reserved.
13 #include <linux/nvmem-consumer.h>
14 #include <linux/nvmem-provider.h>
54 { .compatible = "nvidia,tegra20-car", },
55 { .compatible = "nvidia,tegra30-car", },
56 { .compatible = "nvidia,tegra114-car", },
57 { .compatible = "nvidia,tegra124-car", },
58 { .compatible = "nvidia,tegra132-car", },
59 { .compatible = "nvidia,tegra210-car", },
[all …]
/linux-6.14.4/arch/arm64/include/asm/
Dkgdb.h1 /* SPDX-License-Identifier: GPL-2.0-only */
15 #include <asm/debug-monitors.h>
33 * General purpose regs:
34 * r0-r30: 64 bit
38 * FPU regs:
39 * f0-f31: 128 bit
45 * Architecture Reference Manual that claimed "SPSR_ELx is a 32-bit register".
46 * and, as a result, allocated only 32-bits for the PSTATE in the remote
49 * Unfortunately "is a 32-bit register" has a very special meaning for
53 * little for people who don't spend their spare time reading ARM architecture
[all …]
/linux-6.14.4/drivers/thermal/tegra/
Dtegra30-tsensor.c1 // SPDX-License-Identifier: GPL-2.0
9 * Copyright (C) 2021 GRATE-DRIVER project
74 void __iomem *regs; member
81 void __iomem *regs; member
95 err = reset_control_assert(ts->rst); in tegra_tsensor_hw_enable()
97 dev_err(ts->dev, "failed to assert hardware reset: %d\n", err); in tegra_tsensor_hw_enable()
101 err = clk_prepare_enable(ts->clk); in tegra_tsensor_hw_enable()
103 dev_err(ts->dev, "failed to enable clock: %d\n", err); in tegra_tsensor_hw_enable()
109 err = reset_control_deassert(ts->rst); in tegra_tsensor_hw_enable()
111 dev_err(ts->dev, "failed to deassert hardware reset: %d\n", err); in tegra_tsensor_hw_enable()
[all …]
/linux-6.14.4/arch/m68k/include/asm/
Ddvma.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * include/asm-m68k/dma.h
16 #define DVMA_PAGE_MASK (~(DVMA_PAGE_SIZE-1))
43 #define DVMA_SIZE (DVMA_END-DVMA_START)
47 /* empirical kludge -- dvma regions only seem to work right on 0x10000
50 #define DVMA_ALIGN(addr) (((addr)+DVMA_REGION_SIZE-1) & \
51 ~(DVMA_REGION_SIZE-1))
53 /* virt <-> phys conversions */
77 #define DVMA_SIZE (DVMA_END-DVMA_START)
80 #define IOMMU_ENTRIES (IOMMU_TOTAL_ENTRIES - 0x80)
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
Dsmu13_driver_if_v13_0_6.h122 // GCEA Pin UE_ERR regs
137 // GCEA Pin, UE_EDC regs
150 // SOC error codes 40-42 are common with ERR_CODE_e
171 uint32_t Spare[8]; member
197 //0-23 SOC, 24-26 SOCIO, 27-29 SOC
205 //0-27 GFX, 28-29 SOC
212 // Defines used for IH-based thermal interrupts to GFX driver - A/X only
216 //thermal over-temp mask defines for IH interrupt to host
/linux-6.14.4/drivers/edac/
Di5400_edac.c18 * Intel 5400 Chipset Memory Controller Hub (MCH) - Datasheet
21 * This Memory Controller manages DDR2 FB-DIMMs. It has 2 branches, each with
22 * 2 channels operating in lockstep no-mirror mode. Each channel can have up to
83 #define FERR_FAT_FBDCHAN (3<<28) /* channel index where the highest-order error occurred */
88 /* Non-fatal error register */
140 * Error masks are according with Table 5-17 of i5400 datasheet
144 EMASK_M1 = 1<<0, /* Memory Write error on non-redundant retry */
145 EMASK_M2 = 1<<1, /* Memory or FB-DIMM configuration CRC read error */
148 EMASK_M5 = 1<<4, /* Aliased Uncorrectable Non-Mirrored Demand Data ECC */
150 EMASK_M7 = 1<<6, /* Aliased Uncorrectable Resilver- or Spare-Copy Data ECC */
[all …]
Di7300_edac.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * Intel 7300 Chipset Memory Controller Hub (MCH) - Datasheet
48 * Branch 0 - 2 channels: channels 0 and 1 (FDB0 PCI dev 21.0)
49 * Branch 1 - 2 channels: channels 2 and 3 (FDB1 PCI dev 22.0)
106 u16 ambpresent[MAX_CHANNELS]; /* AMB present regs */
151 * memory. From datasheet item 7.3.1 (FB-DIMM technology & organization), it
170 * MTRx - Memory Technology Registers
192 [22] = "Non-Redundant Fast Reset Timeout",
195 [0] = "Memory Write error on non-redundant retry or "
203 [24] = "DIMM-Spare Copy Completed",
[all …]
Di5000_edac.c12 * Intel 5000X Chipset Memory Controller Hub (MCH) - Datasheet
102 /* Non-Retry or redundant Retry errors */
277 * MTRx - Memory Technology Registers
290 /* enables the report of miscellaneous messages as CE errors - default off */
363 u32 ferr_nf_fbd; /* First Errors Non-Fatal */
364 u32 nerr_nf_fbd; /* Next Errors Non-Fatal */
372 * Non-Recoverable Error */
373 u16 nrecmema; /* Non-Recoverable Mem log A */
374 u32 nrecmemb; /* Non-Recoverable Mem log B */
391 pvt = mci->pvt_info; in i5000_get_error_info()
[all …]
/linux-6.14.4/drivers/net/ethernet/sun/
Dcassini.c1 // SPDX-License-Identifier: GPL-2.0+
13 * load balancing (non-VLAN mode)
16 * page-based RX descriptor engine with separate completion rings
22 * -- driver allocates pages at a time and keeps reference counts
24 * -- the upper protocol layers assume that the header is in the skb
27 * -- driver appends the rest of the data pages as frags to skbuffs
29 * -- on page reclamation, the driver swaps the page with a spare page.
37 * TX has 4 queues. currently these queues are used in a round-robin
41 * alternatively, the queues can be configured via use of the all-purpose
49 * encrypted and non-encrypted packets, but we use them for buffering
[all …]
/linux-6.14.4/arch/arm/kernel/
Dunwind.c1 // SPDX-License-Identifier: GPL-2.0-only
69 enum regs { enum
90 /* sign-extend to 32 bits */ \
101 * stop - 1 = last entry
125 addr_prel31 = (addr - (unsigned long)start) & 0x7fffffff; in search_index()
127 while (start < stop - 1) { in search_index()
128 const struct unwind_idx *mid = start + ((stop - start) >> 1); in search_index()
134 if (addr_prel31 - ((unsigned long)mid - (unsigned long)start) < in search_index()
135 mid->addr_offset) in search_index()
139 addr_prel31 -= ((unsigned long)mid - in search_index()
[all …]
/linux-6.14.4/drivers/mfd/
Dtc3589x.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) ST-Ericsson SA 2010
5 * Author: Hanumath Prasad <[email protected]> for ST-Ericsson
6 * Author: Rabin Vincent <[email protected]> for ST-Ericsson
22 * enum tc3589x_version - indicates the TC3589x version
38 * tc3589x_reg_read() - read a single TC3589x register
46 ret = i2c_smbus_read_byte_data(tc3589x->i2c, reg); in tc3589x_reg_read()
48 dev_err(tc3589x->dev, "failed to read reg %#x: %d\n", in tc3589x_reg_read()
56 * tc3589x_reg_write() - write a single TC3589x register
65 ret = i2c_smbus_write_byte_data(tc3589x->i2c, reg, data); in tc3589x_reg_write()
[all …]
/linux-6.14.4/drivers/video/fbdev/
Dsm501fb.c1 // SPDX-License-Identifier: GPL-2.0-only
22 #include <linux/dma-mapping.h>
40 #include <linux/sm501-regs.h>
44 static char *fb_mode = "640x480-16@60";
94 void __iomem *regs; /* remapped registers */ member
101 /* per-framebuffer private data */
120 return var->xres + var->left_margin + in h_total()
121 var->right_margin + var->hsync_len; in h_total()
126 return var->yres + var->upper_margin + in v_total()
127 var->lower_margin + var->vsync_len; in v_total()
[all …]
/linux-6.14.4/drivers/remoteproc/
Dqcom_q6v5_mss.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Qualcomm self-authenticating modem subsystem remoteproc driver
7 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
13 #include <linux/dma-mapping.h>
261 static int q6v5_regulator_init(struct device *dev, struct reg_info *regs, in q6v5_regulator_init() argument
270 regs[i].reg = devm_regulator_get(dev, reg_res[i].supply); in q6v5_regulator_init()
271 if (IS_ERR(regs[i].reg)) in q6v5_regulator_init()
272 return dev_err_probe(dev, PTR_ERR(regs[i].reg), in q6v5_regulator_init()
276 regs[i].uV = reg_res[i].uV; in q6v5_regulator_init()
277 regs[i].uA = reg_res[i].uA; in q6v5_regulator_init()
[all …]

123