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/linux-6.14.4/Documentation/devicetree/bindings/mmc/
Dbrcm,sdhci-brcmstb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/brcm,sdhci-brcmstb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BRCMSTB/BMIPS SDHCI Controller
10 - Al Cooper <[email protected]>
11 - Florian Fainelli <[email protected]>
16 - items:
17 - enum:
18 - brcm,bcm7216-sdhci
[all …]
/linux-6.14.4/arch/mips/boot/dts/brcm/
Dbcm7435.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <175625000>;
42 cpu_intc: interrupt-controller {
43 #address-cells = <0>;
44 compatible = "mti,cpu-interrupt-controller";
46 interrupt-controller;
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Dbcm7425.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <163125000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
[all …]
Dbcm7360.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <375000000>;
24 cpu_intc: interrupt-controller {
25 #address-cells = <0>;
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
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Dbcm7362.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <375000000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
[all …]
Dbcm7346.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <163125000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
[all …]
/linux-6.14.4/drivers/mmc/host/
Dsdhci-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * sdhci-brcmstb.c Support for SDHCI on Broadcom BRCMSTB SoC's
16 #include "sdhci-cqhci.h"
17 #include "sdhci-pltfm.h"
69 if (!(priv->flags & BRCMSTB_PRIV_FLAGS_GATE_CLOCK)) in enable_clock_gating()
81 /* Reset will clear this, so re-enable it */ in brcmstb_reset()
94 * bits, hence access SDHCI_CLOCK_CONTROL register as 32-bit register in brcmstb_sdhci_reset_cmd_data()
108 mmc_hostname(host->mmc), (int)mask); in brcmstb_sdhci_reset_cmd_data()
124 /* Reset will clear this, so re-enable it */ in brcmstb_reset_74165b0()
134 dev_dbg(mmc_dev(mmc), "%s(): Setting HS400-Enhanced-Strobe mode\n", in sdhci_brcmstb_hs400es()
[all …]
DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 obj-$(CONFIG_MMC_ARMMMCI) += armmmci.o
7 armmmci-y := mmci.o
8 armmmci-$(CONFIG_MMC_QCOM_DML) += mmci_qcom_dml.o
9 armmmci-$(CONFIG_MMC_STM32_SDMMC) += mmci_stm32_sdmmc.o
10 obj-$(CONFIG_MMC_PXA) += pxamci.o
11 obj-$(CONFIG_MMC_MXC) += mxcmmc.o
12 obj-$(CONFIG_MMC_MXS) += mxs-mmc.o
13 obj-$(CONFIG_MMC_SDHCI) += sdhci.o
14 obj-$(CONFIG_MMC_SDHCI_UHS2) += sdhci-uhs2.o
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/linux-6.14.4/arch/arm64/boot/dts/broadcom/
Dbcm2712.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #address-cells = <2>;
8 #size-cells = <2>;
10 interrupt-parent = <&gicv2>;
14 clk_osc: clk-osc {
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-output-names = "osc";
18 clock-frequency = <54000000>;
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/linux-6.14.4/
DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-[email protected]
88 F: drivers/scsi/3w-*
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