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/linux-6.14.4/Documentation/devicetree/bindings/soc/qcom/
Dqcom,geni-se.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <[email protected]>
23 - qcom,geni-se-qup
24 - qcom,geni-se-i2c-master-hub
30 clock-names:
38 "#address-cells":
41 "#size-cells":
[all …]
/linux-6.14.4/drivers/clk/imx/
Dclk-imx35.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Sascha Hauer, Pengutronix <s[email protected]>
33 unsigned char arm, ahb, sel; member
37 { .arm = 1, .ahb = 4, .sel = 0},
38 { .arm = 1, .ahb = 3, .sel = 1},
39 { .arm = 2, .ahb = 2, .sel = 0},
40 { .arm = 0, .ahb = 0, .sel = 0},
41 { .arm = 0, .ahb = 0, .sel = 0},
42 { .arm = 0, .ahb = 0, .sel = 0},
43 { .arm = 4, .ahb = 1, .sel = 0},
[all …]
Dclk-imx25.c1 // SPDX-License-Identifier: GPL-2.0-or-later
47 static const char *per_sel_clks[] = { "ahb", "upll", };
48 static const char *cko_sel_clks[] = { "dummy", "osc", "cpu", "ahb",
54 dummy, osc, mpll, upll, mpll_cpu_3_4, cpu_sel, cpu, ahb, usb_div, ipg, enumerator
87 clk[ahb] = imx_clk_divider("ahb", "cpu", ccm(CCM_CCTL), 28, 2); in __mx25_clocks_init()
89 clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); in __mx25_clocks_init()
141 clk[ata_ahb] = imx_clk_gate("ata_ahb", "ahb", ccm(CCM_CGCR0), 16); in __mx25_clocks_init()
143 clk[csi_ahb] = imx_clk_gate("csi_ahb", "ahb", ccm(CCM_CGCR0), 18); in __mx25_clocks_init()
144 clk[emi_ahb] = imx_clk_gate("emi_ahb", "ahb", ccm(CCM_CGCR0), 19); in __mx25_clocks_init()
145 clk[esai_ahb] = imx_clk_gate("esai_ahb", "ahb", ccm(CCM_CGCR0), 20); in __mx25_clocks_init()
[all …]
Dclk-imx31.c1 // SPDX-License-Identifier: GPL-2.0-or-later
39 dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, enumerator
63 clk[ahb] = imx_clk_divider("ahb", "mcu_main", base + MXC_CCM_PDR0, 3, 3); in _mx31_clocks_init()
64 clk[nfc] = imx_clk_divider("nfc", "ahb", base + MXC_CCM_PDR0, 8, 3); in _mx31_clocks_init()
65 clk[ipg] = imx_clk_divider("ipg", "ahb", base + MXC_CCM_PDR0, 6, 2); in _mx31_clocks_init()
82 clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MXC_CCM_CGR0, 14); in _mx31_clocks_init()
100 clk[usb_gate] = imx_clk_gate2("usb_gate", "ahb", base + MXC_CCM_CGR1, 18); in _mx31_clocks_init()
111 clk[emi_gate] = imx_clk_gate2("emi_gate", "ahb", base + MXC_CCM_CGR2, 8); in _mx31_clocks_init()
112 clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MXC_CCM_CGR2, 10); in _mx31_clocks_init()
130 for_each_compatible_node(osc_np, NULL, "fixed-clock") { in mx31_clocks_init_dt()
[all …]
/linux-6.14.4/drivers/soc/versatile/
Dsoc-integrator.c1 // SPDX-License-Identifier: GPL-2.0-only
21 { .compatible = "arm,core-module-integrator", },
29 return "ASB little-endian"; in integrator_arch_str()
31 return "AHB little-endian"; in integrator_arch_str()
33 return "AHB-Lite system bus, bi-endian"; in integrator_arch_str()
35 return "AHB"; in integrator_arch_str()
37 return "AHB system bus, ASB processor bus"; in integrator_arch_str()
70 return sprintf(buf, "%s\n", integrator_arch_str(integrator_coreid)); in arch_show()
78 return sprintf(buf, "%s\n", integrator_fpga_str(integrator_coreid)); in fpga_show()
113 return -ENODEV; in integrator_soc_init()
[all …]
/linux-6.14.4/drivers/clk/microchip/
Dclk-mpfs.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved.
7 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/microchip,mpfs-clock.h>
120 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; in mpfs_clk_msspll_recalc_rate()
121 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; in mpfs_clk_msspll_recalc_rate()
159 msspll_hw->base = data->msspll_base; in mpfs_clk_register_mssplls()
160 ret = devm_clk_hw_register(dev, &msspll_hw->hw); in mpfs_clk_register_mssplls()
165 data->hw_data.hws[msspll_hw->id] = &msspll_hw->hw; in mpfs_clk_register_mssplls()
207 msspll_out_hw->output.reg = data->msspll_base + msspll_out_hw->reg_offset; in mpfs_clk_register_msspll_outs()
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/clock/
Dqcom,ipq9574-cmn-pll.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <[email protected]>
11 - Luo Jie <[email protected]>
15 input clock. This reference clock is from the on-board Wi-Fi.
20 PLL block also outputs fixed rate clocks to GCC. The PLL's
27 - qcom,ipq9574-cmn-pll
34 - description: The reference clock. The supported clock rates include
[all …]
/linux-6.14.4/drivers/pci/controller/
Dpci-ixp4xx.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on the IXP4xx arch/arm/mach-ixp4xx/common-pci.c driver
9 * Copyright (C) 2003 Greg Ungerer <gerg@linux-m68k.org>
10 * Copyright (C) 2003-2004 MontaVista Software, Inc.
15 * - Test IO-space access
16 * - DMA support
113 * operates in big-endian or little-endian mode. That means that
114 * readl() and writel() that always use little-endian access
116 * when used in big-endian mode. The accesses to the individual
117 * PCI devices on the other hand, are always little-endian and
[all …]
Dpci-rcar-gen2.c1 // SPDX-License-Identifier: GPL-2.0
3 * pci-rcar-gen2: internal PCI bus support
26 /* AHB-PCI Bridge PCI communication registers */
108 struct rcar_pci *priv = bus->sysdata; in rcar_pci_cfg_base()
114 /* Only one EHCI/OHCI device built-in */ in rcar_pci_cfg_base()
126 iowrite32(val, priv->reg + RCAR_AHBPCI_WIN1_CTR_REG); in rcar_pci_cfg_base()
127 return priv->reg + (slot >> 1) * 0x100 + where; in rcar_pci_cfg_base()
136 struct device *dev = priv->dev; in rcar_pci_err_irq()
137 u32 status = ioread32(priv->reg + RCAR_PCI_INT_STATUS_REG); in rcar_pci_err_irq()
142 /* clear the error(s) */ in rcar_pci_err_irq()
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/crypto/
Dfsl-imx-sahara.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/fsl-imx-sahara.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Steffen Trumtrar <s[email protected]>
15 - fsl,imx27-sahara
16 - fsl,imx53-sahara
23 - description: SAHARA Interrupt for Host 0
24 - description: SAHARA Interrupt for Host 1
29 - description: Sahara IPG clock
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/iommu/
Darm,smmu.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <[email protected]>
11 - Robin Murphy <[email protected]>
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
28 - enum:
29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/bus/
Dfsl,imx8qxp-pixel-link-msi-bus.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <[email protected]>
18 i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks,
19 that is, MSI clock and AHB clock, need to be enabled so that peripherals
30 So, the controller's registers cannot be accessed by SCFW user. Hence,
32 user's point of view.
35 - $ref: simple-pm-bus.yaml#
[all …]
/linux-6.14.4/drivers/usb/host/
Docteon-hcd.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 * Copyright (c) 2003-2010 Cavium Networks ([email protected]). All rights
31 * This Software, including technical data, may be subject to U.S. export
32 * control laws, including the U.S. Export Administration Act and its associated
102 * Core AHB Configuration Register (GAHBCFG)
104 * This register can be used to configure the core after power-on or a change in
105 * mode of operation. This register mainly contains AHB system-related
106 * configuration parameters. The AHB is the processor interface to the O2P USB
126 * @nptxfemplvl: Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)
128 * Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/ata/
Dimx-sata.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/imx-sata.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <[email protected]>
19 - fsl,imx53-ahci
20 - fsl,imx6q-ahci
21 - fsl,imx6qp-ahci
22 - fsl,imx8qm-ahci
33 - description: sata clock
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/display/imx/
Dfsl,imx-lcdc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx-lcdc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sascha Hauer <s[email protected]>
11 - Pengutronix Kernel Team <[email protected]>
16 - enum:
17 - fsl,imx1-fb
18 - fsl,imx21-fb
19 - items:
[all …]
/linux-6.14.4/arch/mips/ath25/
Dar2315_regs.h11 * Copyright (C) 2006-2008 Felix Fietkau <[email protected]>
81 #define AR2315_RESET_MPEGTS_RSVD 0x00000004 /* warm reset MPEG-TS */
82 #define AR2315_RESET_PCIDMA 0x00000008 /* warm reset PCI ahb/dma */
92 /* AHB master arbitration control */
97 #define AR2315_ARB_MPEGTS_RSVD 0x00000004 /* MPEG-TS */
106 #define AR2315_CONFIG_AHB 0x00000001 /* EC-AHB bridge endian */
108 #define AR2315_CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */
128 /* Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0). */
163 #define AR2315_ISR_AHB 0x00000008 /* AHB error */
172 #define AR2315_GISR_MPEGTS_RSVD 0x00000004 /* MPEG-TS */
[all …]
Dar5312.c9 * Copyright (C) 2006-2009 Felix Fietkau <[email protected]>
65 pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n", in ar5312_ahb_err_handler()
68 machine_restart("AHB error"); /* Catastrophic failure */ in ar5312_ahb_err_handler()
96 ar5312_rst_reg_mask(AR5312_IMR, 0, BIT(d->hwirq)); in ar5312_misc_irq_unmask()
102 ar5312_rst_reg_mask(AR5312_IMR, BIT(d->hwirq), 0); in ar5312_misc_irq_mask()
107 .name = "ar5312-misc",
152 if (request_irq(irq, ar5312_ahb_err_handler, 0, "ar5312-ahb-error", in ar5312_arch_init_irq()
154 pr_err("Failed to register ar5312-ahb-error interrupt\n"); in ar5312_arch_init_irq()
168 .end = AR5312_FLASH_BASE + AR5312_FLASH_SIZE - 1,
173 .name = "physmap-flash",
[all …]
/linux-6.14.4/Documentation/ABI/testing/
Ddebugfs-driver-dcc6 hardware if it's ready to receive user configurations.
27 What: /sys/kernel/debug/dcc/.../[list-number]/config
35 write, read-write, and loop type. The lists need to
45 echo R <addr> <n> <bus> >/sys/kernel/debug/dcc/../[list-number]/config
58 The bus type, which can be either 'apb' or 'ahb'.
59 The default is 'ahb' if leaved out.
65 echo W <addr> <n> <bus type> > /sys/kernel/debug/dcc/../[list-number]/config
76 The bus type, which can be either 'apb' or 'ahb'.
78 iii) Read-write instruction
82 echo RW <addr> <n> <mask> > /sys/kernel/debug/dcc/../[list-number]/config
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/net/
Dsnps,dwc-qos-ethernet.txt13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
24 same order. See ../clock/clock-bindings.txt.
25 - clock-names: May contain any/all of the following depending on the IP
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/usb/
Dchipidea,usb2-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/chipidea,usb2-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xu Yang <[email protected]>
25 clock-names:
31 power-domains:
37 reset-names:
40 "#reset-cells":
45 itc-setting:
[all …]
/linux-6.14.4/drivers/net/wireless/ath/ath10k/
Dahb.c1 // SPDX-License-Identifier: ISC
3 * Copyright (c) 2016-2017 Qualcomm Atheros, Inc. All rights reserved.
14 #include "ahb.h"
17 { .compatible = "qcom,ipq4019-wifi",
30 return &ath10k_pci_priv(ar)->ahb[0]; in ath10k_ahb_priv()
37 iowrite32(value, ar_ahb->mem + offset); in ath10k_ahb_write32()
44 return ioread32(ar_ahb->mem + offset); in ath10k_ahb_read32()
51 return ioread32(ar_ahb->gcc_mem + offset); in ath10k_ahb_gcc_read32()
58 iowrite32(value, ar_ahb->tcsr_mem + offset); in ath10k_ahb_tcsr_write32()
65 return ioread32(ar_ahb->tcsr_mem + offset); in ath10k_ahb_tcsr_read32()
[all …]
/linux-6.14.4/arch/arm/boot/dts/allwinner/
Dsun6i-a31.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/thermal/thermal.h>
48 #include <dt-bindings/clock/sun6i-a31-ccu.h>
49 #include <dt-bindings/clock/sun6i-rtc.h>
50 #include <dt-bindings/reset/sun6i-a31-ccu.h>
53 interrupt-parent = <&gic>;
54 #address-cells = <1>;
55 #size-cells = <1>;
[all …]
Dsuniv-f1c100s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
7 #include <dt-bindings/clock/suniv-ccu-f1c100s.h>
8 #include <dt-bindings/reset/suniv-ccu-f1c100s.h>
9 #include <dt-bindings/dma/sun4i-a10.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
14 interrupt-parent = <&intc>;
17 osc24M: clk-24M {
18 #clock-cells = <0>;
19 compatible = "fixed-clock";
[all …]
/linux-6.14.4/drivers/clk/sprd/
Dsc9860-clk.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/sprd,sc9860-clk.h>
25 static CLK_FIXED_FACTOR(fac_4m, "fac-4m", "ext-26m",
27 static CLK_FIXED_FACTOR(fac_2m, "fac-2m", "ext-26m",
29 static CLK_FIXED_FACTOR(fac_1m, "fac-1m", "ext-26m",
31 static CLK_FIXED_FACTOR(fac_250k, "fac-250k", "ext-26m",
33 static CLK_FIXED_FACTOR(fac_rpll0_26m, "rpll0-26m", "ext-26m",
35 static CLK_FIXED_FACTOR(fac_rpll1_26m, "rpll1-26m", "ext-26m",
37 static CLK_FIXED_FACTOR(fac_rco_25m, "rco-25m", "ext-rc0-100m",
[all …]
/linux-6.14.4/arch/arm/boot/dts/nxp/imx/
Dimx35.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 #include "imx35-pinfunc.h"
10 #address-cells = <1>;
11 #size-cells = <1>;
14 * pre-existing /chosen node to be available to insert the
38 #address-cells = <1>;
39 #size-cells = <0>;
42 compatible = "arm,arm1136jf-s";
48 avic: avic-interrupt-controller@68000000 {
49 compatible = "fsl,imx35-avic", "fsl,avic";
[all …]

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