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/linux-6.14.4/Documentation/devicetree/bindings/iio/adc/
Drenesas,rzg2l-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/renesas,rzg2l-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/G2L ADC
10 - Lad Prabhakar <prabhakar.mahadev-[email protected]>
13 A/D Converter block is a successive approximation analog-to-digital converter
14 with a 12-bit accuracy. Up to eight analog input channels can be selected.
15 Conversions can be performed in single or repeat mode. Result of the ADC is
16 stored in a 32-bit data register corresponding to each channel.
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/linux-6.14.4/arch/arm64/boot/dts/renesas/
Dr9a07g043.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/r9a07g043-cpg.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
15 audio_clk1: audio1-clk {
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
19 clock-frequency = <0>;
22 audio_clk2: audio2-clk {
23 compatible = "fixed-clock";
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Dr9a07g054.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g054-cpg.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
23 audio_clk2: audio2-clk {
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Dr9a07g044.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g044-cpg.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
23 audio_clk2: audio2-clk {
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Dr9a08g045.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a08g045-cpg.h>
10 #include <dt-bindings/clock/renesas,r9a08g045-vbattb.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
17 audio_clk1: audio1-clk {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
21 clock-frequency = <0>;
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Drzg2ul-smarc-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
10 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
28 reg_1p8v: regulator-1p8v {
29 compatible = "regulator-fixed";
30 regulator-name = "fixed-1.8V";
31 regulator-min-microvolt = <1800000>;
32 regulator-max-microvolt = <1800000>;
33 regulator-boot-on;
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Drzg2l-smarc-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
10 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
38 reg_1p8v: regulator-1p8v {
39 compatible = "regulator-fixed";
40 regulator-name = "fixed-1.8V";
41 regulator-min-microvolt = <1800000>;
42 regulator-max-microvolt = <1800000>;
43 regulator-boot-on;
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Drzg3s-smarc-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the R9A08G045S33 SMARC Carrier-II's SoM board.
8 #include <dt-bindings/clock/renesas,r9a08g045-vbattb.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
13 * On-board switches' states:
23 * SW_OFF - SD0 is connected to eMMC
24 * SW_ON - SD0 is connected to uSD0 card
26 * SW_OFF - SD2 is connected to SoC
27 * SW_ON - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC
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/linux-6.14.4/drivers/iio/adc/
Drzg2l_adc.c1 // SPDX-License-Identifier: GPL-2.0
7 * Author: Lad Prabhakar <prabhakar.mahadev-[email protected]>
25 #define DRIVER_NAME "rzg2l-adc"
59 * struct rzg2l_adc_hw_params - ADC hardware specific parameters
60 * @default_adsmp: default ADC sampling period (see ADM3 register); index 0 is
62 * @adsmp_mask: ADC sampling period mask (see ADM3 register)
64 * @default_adcmp: default ADC cmp (see ADM3 register)
95 * struct rzg2l_adc_channel - ADC channel descriptor
96 * @name: ADC channel name
97 * @type: ADC channel type
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/linux-6.14.4/drivers/thermal/renesas/
Drzg2l_thermal.c1 // SPDX-License-Identifier: GPL-2.0
50 #define TS_CODE_CAP_TIMES 8 /* Total number of ADC data samples */
67 return ioread32(priv->base + reg); in rzg2l_thermal_read()
73 iowrite32(data, priv->base + reg); in rzg2l_thermal_write()
109 val = ((dsensor - priv->calib1) * (MCELSIUS(165) / in rzg2l_thermal_get_temp()
110 (priv->calib0 - priv->calib1))) - MCELSIUS(40); in rzg2l_thermal_get_temp()
139 return readl_poll_timeout(priv->base + TSU_SS, reg_val, in rzg2l_thermal_init()
146 struct rzg2l_thermal_priv *priv = dev_get_drvdata(&pdev->dev); in rzg2l_thermal_reset_assert_pm_disable_put()
148 pm_runtime_put(&pdev->dev); in rzg2l_thermal_reset_assert_pm_disable_put()
149 pm_runtime_disable(&pdev->dev); in rzg2l_thermal_reset_assert_pm_disable_put()
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/linux-6.14.4/drivers/clk/renesas/
Dr9a08g045-cpg.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/r9a08g045-cpg.h>
16 #include "rzg2l-cpg.h"
295 /* Keep always-on domain on the first position for proper domains registration. */
296 DEF_PD("always-on", R9A08G045_PD_ALWAYS_ON,
329 DEF_PD("usb-phy", R9A08G045_PD_USB_PHY,
355 DEF_PD("adc", R9A08G045_PD_ADC,
/linux-6.14.4/
DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-[email protected]
88 F: drivers/scsi/3w-*
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