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/aosp_15_r20/external/vixl/test/aarch32/
H A Dtest-assembler-cond-rd-operand-rn-ror-amount-a32.cc74 ShiftType ror; member
102 {{vc, r2, r5, ROR, 0}, false, al, "vc r2 r5 ROR 0", "vc_r2_r5_ROR_0"},
103 {{eq, r5, r7, ROR, 0}, false, al, "eq r5 r7 ROR 0", "eq_r5_r7_ROR_0"},
104 {{ge, r3, r2, ROR, 8}, false, al, "ge r3 r2 ROR 8", "ge_r3_r2_ROR_8"},
105 {{cc, r11, r3, ROR, 16}, false, al, "cc r11 r3 ROR 16", "cc_r11_r3_ROR_16"},
106 {{cs, r13, r6, ROR, 0}, false, al, "cs r13 r6 ROR 0", "cs_r13_r6_ROR_0"},
107 {{al, r6, r7, ROR, 16}, false, al, "al r6 r7 ROR 16", "al_r6_r7_ROR_16"},
108 {{le, r12, r12, ROR, 0}, false, al, "le r12 r12 ROR 0", "le_r12_r12_ROR_0"},
109 {{mi, r4, r5, ROR, 16}, false, al, "mi r4 r5 ROR 16", "mi_r4_r5_ROR_16"},
110 {{pl, r9, r2, ROR, 16}, false, al, "pl r9 r2 ROR 16", "pl_r9_r2_ROR_16"},
[all …]
H A Dtest-assembler-cond-rd-operand-rn-ror-amount-t32.cc74 ShiftType ror; member
102 {{al, r0, r0, ROR, 0}, false, al, "al r0 r0 ROR 0", "al_r0_r0_ROR_0"},
103 {{al, r0, r0, ROR, 8}, false, al, "al r0 r0 ROR 8", "al_r0_r0_ROR_8"},
104 {{al, r0, r0, ROR, 16}, false, al, "al r0 r0 ROR 16", "al_r0_r0_ROR_16"},
105 {{al, r0, r0, ROR, 24}, false, al, "al r0 r0 ROR 24", "al_r0_r0_ROR_24"},
106 {{al, r0, r1, ROR, 0}, false, al, "al r0 r1 ROR 0", "al_r0_r1_ROR_0"},
107 {{al, r0, r1, ROR, 8}, false, al, "al r0 r1 ROR 8", "al_r0_r1_ROR_8"},
108 {{al, r0, r1, ROR, 16}, false, al, "al r0 r1 ROR 16", "al_r0_r1_ROR_16"},
109 {{al, r0, r1, ROR, 24}, false, al, "al r0 r1 ROR 24", "al_r0_r1_ROR_24"},
110 {{al, r0, r2, ROR, 0}, false, al, "al r0 r2 ROR 0", "al_r0_r2_ROR_0"},
[all …]
H A Dtest-assembler-cond-rd-rn-operand-rm-ror-amount-t32.cc75 ShiftType ror; member
102 const TestData kTests[] = {{{al, r4, r0, r8, ROR, 16},
105 "al r4 r0 r8 ROR 16",
107 {{al, r14, r13, r12, ROR, 24},
110 "al r14 r13 r12 ROR 24",
112 {{al, r9, r10, r5, ROR, 16},
115 "al r9 r10 r5 ROR 16",
117 {{al, r11, r13, r14, ROR, 8},
120 "al r11 r13 r14 ROR 8",
122 {{al, r3, r12, r11, ROR, 16},
[all …]
H A Dtest-assembler-cond-rd-rn-operand-rm-ror-amount-a32.cc75 ShiftType ror; member
102 const TestData kTests[] = {{{ls, r3, r3, r13, ROR, 0},
105 "ls r3 r3 r13 ROR 0",
107 {{cs, r2, r7, r1, ROR, 16},
110 "cs r2 r7 r1 ROR 16",
112 {{mi, r13, r0, r2, ROR, 8},
115 "mi r13 r0 r2 ROR 8",
117 {{lt, r0, r6, r1, ROR, 8},
120 "lt r0 r6 r1 ROR 8",
122 {{al, r6, r4, r8, ROR, 16},
[all …]
H A Dtest-assembler-cond-rd-operand-rn-shift-amount-1to31-a32.cc104 {{vc, r5, r5, ROR, 10}, false, al, "vc r5 r5 ROR 10", "vc_r5_r5_ROR_10"},
105 {{ne, r3, r4, ROR, 17}, false, al, "ne r3 r4 ROR 17", "ne_r3_r4_ROR_17"},
106 {{cs, r9, r10, ROR, 16}, false, al, "cs r9 r10 ROR 16", "cs_r9_r10_ROR_16"},
107 {{lt, r0, r2, ROR, 29}, false, al, "lt r0 r2 ROR 29", "lt_r0_r2_ROR_29"},
108 {{al, r11, r2, ROR, 23}, false, al, "al r11 r2 ROR 23", "al_r11_r2_ROR_23"},
110 {{eq, r5, r3, ROR, 21}, false, al, "eq r5 r3 ROR 21", "eq_r5_r3_ROR_21"},
111 {{pl, r2, r10, ROR, 13}, false, al, "pl r2 r10 ROR 13", "pl_r2_r10_ROR_13"},
113 {{mi, r11, r10, ROR, 31},
116 "mi r11 r10 ROR 31",
120 {{eq, r10, r11, ROR, 7}, false, al, "eq r10 r11 ROR 7", "eq_r10_r11_ROR_7"},
[all …]
H A Dtest-assembler-cond-rd-operand-rn-shift-amount-1to31-t32.cc104 {{al, r14, r8, ROR, 21}, false, al, "al r14 r8 ROR 21", "al_r14_r8_ROR_21"},
105 {{al, r5, r13, ROR, 4}, false, al, "al r5 r13 ROR 4", "al_r5_r13_ROR_4"},
106 {{al, r0, r3, ROR, 4}, false, al, "al r0 r3 ROR 4", "al_r0_r3_ROR_4"},
107 {{al, r3, r14, ROR, 7}, false, al, "al r3 r14 ROR 7", "al_r3_r14_ROR_7"},
111 {{al, r0, r9, ROR, 17}, false, al, "al r0 r9 ROR 17", "al_r0_r9_ROR_17"},
112 {{al, r11, r3, ROR, 31}, false, al, "al r11 r3 ROR 31", "al_r11_r3_ROR_31"},
113 {{al, r8, r8, ROR, 20}, false, al, "al r8 r8 ROR 20", "al_r8_r8_ROR_20"},
119 {{al, r1, r3, ROR, 27}, false, al, "al r1 r3 ROR 27", "al_r1_r3_ROR_27"},
120 {{al, r9, r10, ROR, 5}, false, al, "al r9 r10 ROR 5", "al_r9_r10_ROR_5"},
121 {{al, r3, r11, ROR, 25}, false, al, "al r3 r11 ROR 25", "al_r3_r11_ROR_25"},
[all …]
H A Dtest-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc121 {{al, r7, r8, r10, ROR, 21},
124 "al r7 r8 r10 ROR 21",
126 {{al, r5, r5, r3, ROR, 12},
129 "al r5 r5 r3 ROR 12",
136 {{al, r9, r10, r11, ROR, 2},
139 "al r9 r10 r11 ROR 2",
151 {{al, r2, r11, r1, ROR, 9},
154 "al r2 r11 r1 ROR 9",
161 {{al, r6, r13, r3, ROR, 1},
164 "al r6 r13 r3 ROR 1",
[all …]
/aosp_15_r20/external/vixl/test/aarch32/traces/
H A Dassembler-cond-rd-rn-operand-rm-ror-amount-uxtab16-a32.h38 0x7d, 0x30, 0xc3, 0x96 // uxtab16 ls r3 r3 r13 ROR 0
41 0x71, 0x28, 0xc7, 0x26 // uxtab16 cs r2 r7 r1 ROR 16
44 0x72, 0xd4, 0xc0, 0x46 // uxtab16 mi r13 r0 r2 ROR 8
47 0x71, 0x04, 0xc6, 0xb6 // uxtab16 lt r0 r6 r1 ROR 8
50 0x78, 0x68, 0xc4, 0xe6 // uxtab16 al r6 r4 r8 ROR 16
53 0x7a, 0x18, 0xc7, 0xc6 // uxtab16 gt r1 r7 r10 ROR 16
56 0x7b, 0xc8, 0xc9, 0x36 // uxtab16 cc r12 r9 r11 ROR 16
59 0x7d, 0x6c, 0xc8, 0x46 // uxtab16 mi r6 r8 r13 ROR 24
62 0x76, 0x98, 0xc1, 0x46 // uxtab16 mi r9 r1 r6 ROR 16
65 0x7e, 0x84, 0xc9, 0xd6 // uxtab16 le r8 r9 r14 ROR 8
[all …]
H A Dassembler-cond-rd-rn-operand-rm-ror-amount-uxtab-a32.h38 0x7d, 0x30, 0xe3, 0x96 // uxtab ls r3 r3 r13 ROR 0
41 0x71, 0x28, 0xe7, 0x26 // uxtab cs r2 r7 r1 ROR 16
44 0x72, 0xd4, 0xe0, 0x46 // uxtab mi r13 r0 r2 ROR 8
47 0x71, 0x04, 0xe6, 0xb6 // uxtab lt r0 r6 r1 ROR 8
50 0x78, 0x68, 0xe4, 0xe6 // uxtab al r6 r4 r8 ROR 16
53 0x7a, 0x18, 0xe7, 0xc6 // uxtab gt r1 r7 r10 ROR 16
56 0x7b, 0xc8, 0xe9, 0x36 // uxtab cc r12 r9 r11 ROR 16
59 0x7d, 0x6c, 0xe8, 0x46 // uxtab mi r6 r8 r13 ROR 24
62 0x76, 0x98, 0xe1, 0x46 // uxtab mi r9 r1 r6 ROR 16
65 0x7e, 0x84, 0xe9, 0xd6 // uxtab le r8 r9 r14 ROR 8
[all …]
H A Dassembler-cond-rd-rn-operand-rm-ror-amount-uxtah-t32.h38 0x10, 0xfa, 0xa8, 0xf4 // uxtah al r4 r0 r8 ROR 16
41 0x1d, 0xfa, 0xbc, 0xfe // uxtah al r14 r13 r12 ROR 24
44 0x1a, 0xfa, 0xa5, 0xf9 // uxtah al r9 r10 r5 ROR 16
47 0x1d, 0xfa, 0x9e, 0xfb // uxtah al r11 r13 r14 ROR 8
50 0x1c, 0xfa, 0xab, 0xf3 // uxtah al r3 r12 r11 ROR 16
53 0x1b, 0xfa, 0xb6, 0xf0 // uxtah al r0 r11 r6 ROR 24
56 0x19, 0xfa, 0xad, 0xf1 // uxtah al r1 r9 r13 ROR 16
59 0x14, 0xfa, 0xab, 0xfe // uxtah al r14 r4 r11 ROR 16
62 0x1d, 0xfa, 0xa5, 0xf2 // uxtah al r2 r13 r5 ROR 16
65 0x11, 0xfa, 0xb0, 0xf9 // uxtah al r9 r1 r0 ROR 24
[all …]
H A Dassembler-cond-rd-rn-operand-rm-ror-amount-sxtab-t32.h38 0x40, 0xfa, 0xa8, 0xf4 // sxtab al r4 r0 r8 ROR 16
41 0x4d, 0xfa, 0xbc, 0xfe // sxtab al r14 r13 r12 ROR 24
44 0x4a, 0xfa, 0xa5, 0xf9 // sxtab al r9 r10 r5 ROR 16
47 0x4d, 0xfa, 0x9e, 0xfb // sxtab al r11 r13 r14 ROR 8
50 0x4c, 0xfa, 0xab, 0xf3 // sxtab al r3 r12 r11 ROR 16
53 0x4b, 0xfa, 0xb6, 0xf0 // sxtab al r0 r11 r6 ROR 24
56 0x49, 0xfa, 0xad, 0xf1 // sxtab al r1 r9 r13 ROR 16
59 0x44, 0xfa, 0xab, 0xfe // sxtab al r14 r4 r11 ROR 16
62 0x4d, 0xfa, 0xa5, 0xf2 // sxtab al r2 r13 r5 ROR 16
65 0x41, 0xfa, 0xb0, 0xf9 // sxtab al r9 r1 r0 ROR 24
[all …]
H A Dassembler-cond-rd-operand-rn-ror-amount-uxtb-a32.h38 0x75, 0x20, 0xef, 0x76 // uxtb vc r2 r5 ROR 0
41 0x77, 0x50, 0xef, 0x06 // uxtb eq r5 r7 ROR 0
44 0x72, 0x34, 0xef, 0xa6 // uxtb ge r3 r2 ROR 8
47 0x73, 0xb8, 0xef, 0x36 // uxtb cc r11 r3 ROR 16
50 0x76, 0xd0, 0xef, 0x26 // uxtb cs r13 r6 ROR 0
53 0x77, 0x68, 0xef, 0xe6 // uxtb al r6 r7 ROR 16
56 0x7c, 0xc0, 0xef, 0xd6 // uxtb le r12 r12 ROR 0
59 0x75, 0x48, 0xef, 0x46 // uxtb mi r4 r5 ROR 16
62 0x72, 0x98, 0xef, 0x56 // uxtb pl r9 r2 ROR 16
65 0x7b, 0x54, 0xef, 0x66 // uxtb vs r5 r11 ROR 8
[all …]
H A Dassembler-cond-rd-rn-operand-rm-ror-amount-uxtab16-t32.h38 0x30, 0xfa, 0xa8, 0xf4 // uxtab16 al r4 r0 r8 ROR 16
41 0x3d, 0xfa, 0xbc, 0xfe // uxtab16 al r14 r13 r12 ROR 24
44 0x3a, 0xfa, 0xa5, 0xf9 // uxtab16 al r9 r10 r5 ROR 16
47 0x3d, 0xfa, 0x9e, 0xfb // uxtab16 al r11 r13 r14 ROR 8
50 0x3c, 0xfa, 0xab, 0xf3 // uxtab16 al r3 r12 r11 ROR 16
53 0x3b, 0xfa, 0xb6, 0xf0 // uxtab16 al r0 r11 r6 ROR 24
56 0x39, 0xfa, 0xad, 0xf1 // uxtab16 al r1 r9 r13 ROR 16
59 0x34, 0xfa, 0xab, 0xfe // uxtab16 al r14 r4 r11 ROR 16
62 0x3d, 0xfa, 0xa5, 0xf2 // uxtab16 al r2 r13 r5 ROR 16
65 0x31, 0xfa, 0xb0, 0xf9 // uxtab16 al r9 r1 r0 ROR 24
[all …]
H A Dassembler-cond-rd-rn-operand-rm-ror-amount-sxtah-t32.h38 0x00, 0xfa, 0xa8, 0xf4 // sxtah al r4 r0 r8 ROR 16
41 0x0d, 0xfa, 0xbc, 0xfe // sxtah al r14 r13 r12 ROR 24
44 0x0a, 0xfa, 0xa5, 0xf9 // sxtah al r9 r10 r5 ROR 16
47 0x0d, 0xfa, 0x9e, 0xfb // sxtah al r11 r13 r14 ROR 8
50 0x0c, 0xfa, 0xab, 0xf3 // sxtah al r3 r12 r11 ROR 16
53 0x0b, 0xfa, 0xb6, 0xf0 // sxtah al r0 r11 r6 ROR 24
56 0x09, 0xfa, 0xad, 0xf1 // sxtah al r1 r9 r13 ROR 16
59 0x04, 0xfa, 0xab, 0xfe // sxtah al r14 r4 r11 ROR 16
62 0x0d, 0xfa, 0xa5, 0xf2 // sxtah al r2 r13 r5 ROR 16
65 0x01, 0xfa, 0xb0, 0xf9 // sxtah al r9 r1 r0 ROR 24
[all …]
H A Dassembler-cond-rd-operand-rn-ror-amount-uxth-a32.h38 0x75, 0x20, 0xff, 0x76 // uxth vc r2 r5 ROR 0
41 0x77, 0x50, 0xff, 0x06 // uxth eq r5 r7 ROR 0
44 0x72, 0x34, 0xff, 0xa6 // uxth ge r3 r2 ROR 8
47 0x73, 0xb8, 0xff, 0x36 // uxth cc r11 r3 ROR 16
50 0x76, 0xd0, 0xff, 0x26 // uxth cs r13 r6 ROR 0
53 0x77, 0x68, 0xff, 0xe6 // uxth al r6 r7 ROR 16
56 0x7c, 0xc0, 0xff, 0xd6 // uxth le r12 r12 ROR 0
59 0x75, 0x48, 0xff, 0x46 // uxth mi r4 r5 ROR 16
62 0x72, 0x98, 0xff, 0x56 // uxth pl r9 r2 ROR 16
65 0x7b, 0x54, 0xff, 0x66 // uxth vs r5 r11 ROR 8
[all …]
H A Dassembler-cond-rd-rn-operand-rm-ror-amount-sxtab16-t32.h38 0x20, 0xfa, 0xa8, 0xf4 // sxtab16 al r4 r0 r8 ROR 16
41 0x2d, 0xfa, 0xbc, 0xfe // sxtab16 al r14 r13 r12 ROR 24
44 0x2a, 0xfa, 0xa5, 0xf9 // sxtab16 al r9 r10 r5 ROR 16
47 0x2d, 0xfa, 0x9e, 0xfb // sxtab16 al r11 r13 r14 ROR 8
50 0x2c, 0xfa, 0xab, 0xf3 // sxtab16 al r3 r12 r11 ROR 16
53 0x2b, 0xfa, 0xb6, 0xf0 // sxtab16 al r0 r11 r6 ROR 24
56 0x29, 0xfa, 0xad, 0xf1 // sxtab16 al r1 r9 r13 ROR 16
59 0x24, 0xfa, 0xab, 0xfe // sxtab16 al r14 r4 r11 ROR 16
62 0x2d, 0xfa, 0xa5, 0xf2 // sxtab16 al r2 r13 r5 ROR 16
65 0x21, 0xfa, 0xb0, 0xf9 // sxtab16 al r9 r1 r0 ROR 24
[all …]
H A Dassembler-cond-rd-operand-rn-ror-amount-sxth-a32.h38 0x75, 0x20, 0xbf, 0x76 // sxth vc r2 r5 ROR 0
41 0x77, 0x50, 0xbf, 0x06 // sxth eq r5 r7 ROR 0
44 0x72, 0x34, 0xbf, 0xa6 // sxth ge r3 r2 ROR 8
47 0x73, 0xb8, 0xbf, 0x36 // sxth cc r11 r3 ROR 16
50 0x76, 0xd0, 0xbf, 0x26 // sxth cs r13 r6 ROR 0
53 0x77, 0x68, 0xbf, 0xe6 // sxth al r6 r7 ROR 16
56 0x7c, 0xc0, 0xbf, 0xd6 // sxth le r12 r12 ROR 0
59 0x75, 0x48, 0xbf, 0x46 // sxth mi r4 r5 ROR 16
62 0x72, 0x98, 0xbf, 0x56 // sxth pl r9 r2 ROR 16
65 0x7b, 0x54, 0xbf, 0x66 // sxth vs r5 r11 ROR 8
[all …]
H A Dassembler-cond-rd-rn-operand-rm-ror-amount-uxtab-t32.h38 0x50, 0xfa, 0xa8, 0xf4 // uxtab al r4 r0 r8 ROR 16
41 0x5d, 0xfa, 0xbc, 0xfe // uxtab al r14 r13 r12 ROR 24
44 0x5a, 0xfa, 0xa5, 0xf9 // uxtab al r9 r10 r5 ROR 16
47 0x5d, 0xfa, 0x9e, 0xfb // uxtab al r11 r13 r14 ROR 8
50 0x5c, 0xfa, 0xab, 0xf3 // uxtab al r3 r12 r11 ROR 16
53 0x5b, 0xfa, 0xb6, 0xf0 // uxtab al r0 r11 r6 ROR 24
56 0x59, 0xfa, 0xad, 0xf1 // uxtab al r1 r9 r13 ROR 16
59 0x54, 0xfa, 0xab, 0xfe // uxtab al r14 r4 r11 ROR 16
62 0x5d, 0xfa, 0xa5, 0xf2 // uxtab al r2 r13 r5 ROR 16
65 0x51, 0xfa, 0xb0, 0xf9 // uxtab al r9 r1 r0 ROR 24
[all …]
H A Dassembler-cond-rd-operand-rn-ror-amount-sxtb-a32.h38 0x75, 0x20, 0xaf, 0x76 // sxtb vc r2 r5 ROR 0
41 0x77, 0x50, 0xaf, 0x06 // sxtb eq r5 r7 ROR 0
44 0x72, 0x34, 0xaf, 0xa6 // sxtb ge r3 r2 ROR 8
47 0x73, 0xb8, 0xaf, 0x36 // sxtb cc r11 r3 ROR 16
50 0x76, 0xd0, 0xaf, 0x26 // sxtb cs r13 r6 ROR 0
53 0x77, 0x68, 0xaf, 0xe6 // sxtb al r6 r7 ROR 16
56 0x7c, 0xc0, 0xaf, 0xd6 // sxtb le r12 r12 ROR 0
59 0x75, 0x48, 0xaf, 0x46 // sxtb mi r4 r5 ROR 16
62 0x72, 0x98, 0xaf, 0x56 // sxtb pl r9 r2 ROR 16
65 0x7b, 0x54, 0xaf, 0x66 // sxtb vs r5 r11 ROR 8
[all …]
H A Dassembler-cond-rd-rn-operand-rm-ror-amount-sxtah-a32.h38 0x7d, 0x30, 0xb3, 0x96 // sxtah ls r3 r3 r13 ROR 0
41 0x71, 0x28, 0xb7, 0x26 // sxtah cs r2 r7 r1 ROR 16
44 0x72, 0xd4, 0xb0, 0x46 // sxtah mi r13 r0 r2 ROR 8
47 0x71, 0x04, 0xb6, 0xb6 // sxtah lt r0 r6 r1 ROR 8
50 0x78, 0x68, 0xb4, 0xe6 // sxtah al r6 r4 r8 ROR 16
53 0x7a, 0x18, 0xb7, 0xc6 // sxtah gt r1 r7 r10 ROR 16
56 0x7b, 0xc8, 0xb9, 0x36 // sxtah cc r12 r9 r11 ROR 16
59 0x7d, 0x6c, 0xb8, 0x46 // sxtah mi r6 r8 r13 ROR 24
62 0x76, 0x98, 0xb1, 0x46 // sxtah mi r9 r1 r6 ROR 16
65 0x7e, 0x84, 0xb9, 0xd6 // sxtah le r8 r9 r14 ROR 8
[all …]
H A Dassembler-cond-rd-rn-operand-rm-ror-amount-uxtah-a32.h38 0x7d, 0x30, 0xf3, 0x96 // uxtah ls r3 r3 r13 ROR 0
41 0x71, 0x28, 0xf7, 0x26 // uxtah cs r2 r7 r1 ROR 16
44 0x72, 0xd4, 0xf0, 0x46 // uxtah mi r13 r0 r2 ROR 8
47 0x71, 0x04, 0xf6, 0xb6 // uxtah lt r0 r6 r1 ROR 8
50 0x78, 0x68, 0xf4, 0xe6 // uxtah al r6 r4 r8 ROR 16
53 0x7a, 0x18, 0xf7, 0xc6 // uxtah gt r1 r7 r10 ROR 16
56 0x7b, 0xc8, 0xf9, 0x36 // uxtah cc r12 r9 r11 ROR 16
59 0x7d, 0x6c, 0xf8, 0x46 // uxtah mi r6 r8 r13 ROR 24
62 0x76, 0x98, 0xf1, 0x46 // uxtah mi r9 r1 r6 ROR 16
65 0x7e, 0x84, 0xf9, 0xd6 // uxtah le r8 r9 r14 ROR 8
[all …]
H A Dassembler-cond-rd-rn-operand-rm-ror-amount-sxtab16-a32.h38 0x7d, 0x30, 0x83, 0x96 // sxtab16 ls r3 r3 r13 ROR 0
41 0x71, 0x28, 0x87, 0x26 // sxtab16 cs r2 r7 r1 ROR 16
44 0x72, 0xd4, 0x80, 0x46 // sxtab16 mi r13 r0 r2 ROR 8
47 0x71, 0x04, 0x86, 0xb6 // sxtab16 lt r0 r6 r1 ROR 8
50 0x78, 0x68, 0x84, 0xe6 // sxtab16 al r6 r4 r8 ROR 16
53 0x7a, 0x18, 0x87, 0xc6 // sxtab16 gt r1 r7 r10 ROR 16
56 0x7b, 0xc8, 0x89, 0x36 // sxtab16 cc r12 r9 r11 ROR 16
59 0x7d, 0x6c, 0x88, 0x46 // sxtab16 mi r6 r8 r13 ROR 24
62 0x76, 0x98, 0x81, 0x46 // sxtab16 mi r9 r1 r6 ROR 16
65 0x7e, 0x84, 0x89, 0xd6 // sxtab16 le r8 r9 r14 ROR 8
[all …]
H A Dassembler-cond-rd-rn-operand-rm-ror-amount-sxtab-a32.h38 0x7d, 0x30, 0xa3, 0x96 // sxtab ls r3 r3 r13 ROR 0
41 0x71, 0x28, 0xa7, 0x26 // sxtab cs r2 r7 r1 ROR 16
44 0x72, 0xd4, 0xa0, 0x46 // sxtab mi r13 r0 r2 ROR 8
47 0x71, 0x04, 0xa6, 0xb6 // sxtab lt r0 r6 r1 ROR 8
50 0x78, 0x68, 0xa4, 0xe6 // sxtab al r6 r4 r8 ROR 16
53 0x7a, 0x18, 0xa7, 0xc6 // sxtab gt r1 r7 r10 ROR 16
56 0x7b, 0xc8, 0xa9, 0x36 // sxtab cc r12 r9 r11 ROR 16
59 0x7d, 0x6c, 0xa8, 0x46 // sxtab mi r6 r8 r13 ROR 24
62 0x76, 0x98, 0xa1, 0x46 // sxtab mi r9 r1 r6 ROR 16
65 0x7e, 0x84, 0xa9, 0xd6 // sxtab le r8 r9 r14 ROR 8
[all …]
H A Dassembler-cond-rd-operand-rn-ror-amount-sxtb16-a32.h38 0x75, 0x20, 0x8f, 0x76 // sxtb16 vc r2 r5 ROR 0
41 0x77, 0x50, 0x8f, 0x06 // sxtb16 eq r5 r7 ROR 0
44 0x72, 0x34, 0x8f, 0xa6 // sxtb16 ge r3 r2 ROR 8
47 0x73, 0xb8, 0x8f, 0x36 // sxtb16 cc r11 r3 ROR 16
50 0x76, 0xd0, 0x8f, 0x26 // sxtb16 cs r13 r6 ROR 0
53 0x77, 0x68, 0x8f, 0xe6 // sxtb16 al r6 r7 ROR 16
56 0x7c, 0xc0, 0x8f, 0xd6 // sxtb16 le r12 r12 ROR 0
59 0x75, 0x48, 0x8f, 0x46 // sxtb16 mi r4 r5 ROR 16
62 0x72, 0x98, 0x8f, 0x56 // sxtb16 pl r9 r2 ROR 16
65 0x7b, 0x54, 0x8f, 0x66 // sxtb16 vs r5 r11 ROR 8
[all …]
H A Dassembler-cond-rd-operand-rn-ror-amount-uxtb16-a32.h38 0x75, 0x20, 0xcf, 0x76 // uxtb16 vc r2 r5 ROR 0
41 0x77, 0x50, 0xcf, 0x06 // uxtb16 eq r5 r7 ROR 0
44 0x72, 0x34, 0xcf, 0xa6 // uxtb16 ge r3 r2 ROR 8
47 0x73, 0xb8, 0xcf, 0x36 // uxtb16 cc r11 r3 ROR 16
50 0x76, 0xd0, 0xcf, 0x26 // uxtb16 cs r13 r6 ROR 0
53 0x77, 0x68, 0xcf, 0xe6 // uxtb16 al r6 r7 ROR 16
56 0x7c, 0xc0, 0xcf, 0xd6 // uxtb16 le r12 r12 ROR 0
59 0x75, 0x48, 0xcf, 0x46 // uxtb16 mi r4 r5 ROR 16
62 0x72, 0x98, 0xcf, 0x56 // uxtb16 pl r9 r2 ROR 16
65 0x7b, 0x54, 0xcf, 0x66 // uxtb16 vs r5 r11 ROR 8
[all …]

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