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/linux-6.14.4/Documentation/devicetree/bindings/display/rockchip/
Drockchip-drm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only)
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip-drm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip DRM master device
10 - Sandy Huang <hjc@rock-chips.com>
11 - Heiko Stuebner <[email protected]>
14 The Rockchip DRM master device is a virtual device needed to list all
15 vop devices or other display interface nodes that comprise the
20 const: rockchip,display-subsystem
[all …]
Drockchip-vop.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip-vop.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC display controller (VOP)
10 VOP (Video Output Processor) is the display controller for the Rockchip
15 - Sandy Huang <hjc@rock-chips.com>
16 - Heiko Stuebner <[email protected]>
21 - rockchip,px30-vop-big
22 - rockchip,px30-vop-lit
[all …]
Drockchip,analogix-dp.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,analogix-dp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip specific extensions to the Analogix Display Port
10 - Sandy Huang <hjc@rock-chips.com>
11 - Heiko Stuebner <[email protected]>
16 - rockchip,rk3288-dp
17 - rockchip,rk3399-edp
23 clock-names:
[all …]
Drockchip-vop2.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC display controller (VOP2)
10 VOP2 (Video Output Processor v2) is the display controller for the Rockchip
15 - Sandy Huang <hjc@rock-chips.com>
16 - Heiko Stuebner <[email protected]>
21 - rockchip,rk3566-vop
22 - rockchip,rk3568-vop
[all …]
Drockchip,dw-mipi-dsi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-mipi-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip specific extensions to the Synopsys Designware MIPI DSI
10 - Sandy Huang <hjc@rock-chips.com>
11 - Heiko Stuebner <[email protected]>
16 - enum:
17 - rockchip,px30-mipi-dsi
18 - rockchip,rk3128-mipi-dsi
[all …]
Drockchip,rk3588-mipi-dsi2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip specific extensions to the Synopsys Designware MIPI DSI2
10 - Heiko Stuebner <[email protected]>
15 - rockchip,rk3588-mipi-dsi2
26 clock-names:
28 - const: pclk
29 - const: sys
[all …]
Drockchip,rk3588-dw-hdmi-qp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,rk3588-dw-hdmi-qp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip DW HDMI QP TX Encoder
10 - Cristian Ciocaltea <[email protected]>
13 Rockchip RK3588 SoC integrates the Synopsys DesignWare HDMI QP TX controller
18 * Display Stream Compression (DSC)
23 * Multi-stream audio
27 - $ref: /schemas/sound/dai-common.yaml#
[all …]
Drockchip,lvds.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,lvds.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip low-voltage differential signal (LVDS) transmitter
10 - Sandy Huang <hjc@rock-chips.com>
11 - Heiko Stuebner <[email protected]>
16 - rockchip,px30-lvds
17 - rockchip,rk3288-lvds
25 clock-names:
[all …]
Drockchip,inno-hdmi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,inno-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip Innosilicon HDMI controller
10 - Sandy Huang <hjc@rock-chips.com>
11 - Heiko Stuebner <[email protected]>
16 - rockchip,rk3036-inno-hdmi
17 - rockchip,rk3128-inno-hdmi
28 - description: The HDMI controller main clock
[all …]
Drockchip,rk3066-hdmi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,rk3066-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip rk3066 HDMI controller
10 - Sandy Huang <hjc@rock-chips.com>
11 - Heiko Stuebner <[email protected]>
14 - $ref: /schemas/sound/dai-common.yaml#
18 const: rockchip,rk3066-hdmi
29 clock-names:
[all …]
Drockchip,dw-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip DWC HDMI TX Encoder
10 - Mark Yao <[email protected]>
17 - $ref: ../bridge/synopsys,dw-hdmi.yaml#
18 - $ref: /schemas/sound/dai-common.yaml#
23 - rockchip,rk3228-dw-hdmi
24 - rockchip,rk3288-dw-hdmi
[all …]
Dcdn-dp-rockchip.txt1 Rockchip RK3399 specific extensions to the cdn Display Port
5 - compatible: must be "rockchip,rk3399-cdn-dp"
7 - reg: physical base address of the controller and length
9 - clocks: from common clock binding: handle to dp clock.
11 - clock-names: from common clock binding:
12 Required elements: "core-clk" "pclk" "spdif" "grf"
14 - resets : a list of phandle + reset specifier pairs
15 - reset-names : string of reset names
17 - power-domains : power-domain property defined with a phandle
19 - assigned-clocks: main clock, should be <&cru SCLK_DP_CORE>
[all …]
/linux-6.14.4/drivers/phy/rockchip/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Rockchip platforms
6 tristate "Rockchip Display Port PHY Driver"
10 Enable this to support the Rockchip Display Port PHY.
13 tristate "Rockchip MIPI Synopsys DPHY RX0 driver"
18 Enable this to support the Rockchip MIPI Synopsys DPHY RX0
19 associated to the Rockchip ISP module present in RK3399 SoCs.
22 will be called phy-rockchip-dphy-rx0.
25 tristate "Rockchip EMMC PHY Driver"
29 Enable this to support the Rockchip EMMC PHY.
[all …]
/linux-6.14.4/drivers/gpu/drm/ci/
Dtest.yml1 .test-rules:
3 - if: '$FD_FARM == "offline" && $RUNNER_TAG =~ /^google-freedreno-/'
5 - if: '$COLLABORA_FARM == "offline" && $RUNNER_TAG =~ /^mesa-ci-x86-64-lava-/'
7 - !reference [.no_scheduled_pipelines-rules, rules]
8 - when: on_success
10 .lava-test:
12 - .test-rules
16 - rm -rf install
17 - tar -xf artifacts/install.tar
18 - mv install/* artifacts/.
[all …]
/linux-6.14.4/arch/arm64/boot/dts/rockchip/
Drk3568-wolfvision-pf5-display.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
8 /dts-v1/;
11 #include <dt-bindings/clock/rk3568-cru.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/pinctrl/rockchip.h>
15 #include <dt-bindings/soc/rockchip,vop2.h>
19 compatible = "pwm-backlight";
20 brightness-levels = <0 255>;
21 default-brightness-level = <255>;
[all …]
Drk3399-nanopi-r4s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * FriendlyElec NanoPC-R4 board device tree source
15 /dts-v1/;
17 #include "rk3399-nanopi4.dtsi"
20 /delete-node/ display-subsystem;
22 gpio-leds {
23 pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
25 /delete-node/ led-0;
27 lan_led: led-lan {
32 sys_led: led-sys {
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/spi/
Dspi-rockchip.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-rockchip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SPI Controller
10 The Rockchip SPI controller is used to interface with various devices such
11 as flash and display controllers using the SPI communication interface.
14 - $ref: spi-controller.yaml#
17 - Heiko Stuebner <[email protected]>
23 - const: rockchip,rk3036-spi
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/phy/
Drockchip,rk3288-dp-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,rk3288-dp-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip specific extensions to the Analogix Display Port PHY
10 - Heiko Stuebner <[email protected]>
14 const: rockchip,rk3288-dp-phy
19 clock-names:
22 "#phy-cells":
26 - compatible
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/clock/
Drockchip,rk3288-cru.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/clock/rockchip,rk3288-cru.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip RK3288 Clock and Reset Unit (CRU)
10 - Elaine Zhang <zhangqing@rock-chips.com>
11 - Heiko Stuebner <[email protected]>
19 different so another dt-compatible is available. Noticed that it is only
25 preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
31 clock-output-names:
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/soc/rockchip/
Dgrf.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/soc/rockchip/grf.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip General Register Files (GRF)
10 - Heiko Stuebner <[email protected]>
15 - items:
16 - enum:
17 - rockchip,rk3288-sgrf
18 - rockchip,rk3566-pipe-grf
[all …]
/linux-6.14.4/drivers/gpu/drm/rockchip/
Danalogix_dp-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Rockchip SoC DP (Display Port) interface driver.
5 * Copyright (C) Rockchip Electronics Co., Ltd.
6 * Author: Andy Yan <andy.yan@rock-chips.com>
7 * Yakir Yang <ykk@rock-chips.com>
8 * Jeff Chen <jeff.chen@rock-chips.com>
24 #include <drm/display/drm_dp_helper.h>
45 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips
89 reset_control_assert(dp->rst); in rockchip_dp_pre_init()
91 reset_control_deassert(dp->rst); in rockchip_dp_pre_init()
[all …]
/linux-6.14.4/arch/arm/boot/dts/rockchip/
Drv1108-elgin-r1.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
13 compatible = "elgin,rv1108-r1", "rockchip,rv1108";
25 stdout-path = "serial2:1500000n8";
28 vcc_sys: regulator-vsys {
29 compatible = "regulator-fixed";
30 regulator-name = "vsys";
31 regulator-min-microvolt = <5000000>;
32 regulator-max-microvolt = <5000000>;
33 regulator-boot-on;
[all …]
Drk3188.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3188-cru.h>
10 #include <dt-bindings/power/rk3188-power.h>
14 compatible = "rockchip,rk3188";
17 #address-cells = <1>;
18 #size-cells = <0>;
19 enable-method = "rockchip,rk3066-smp";
23 compatible = "arm,cortex-a9";
[all …]
Drk3066a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3066a-cru.h>
10 #include <dt-bindings/power/rk3066-power.h>
14 compatible = "rockchip,rk3066a";
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "rockchip,rk3066-smp";
28 compatible = "arm,cortex-a9";
[all …]
Drk3188-bqedison2qc.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/i2c/i2c.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
14 model = "BQ Edison2 Quad-Core";
15 compatible = "mundoreader,bq-edison2qc", "rockchip,rk3188";
29 compatible = "pwm-backlight";
30 power-supply = <&vsys>;
34 gpio-keys {
[all …]

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