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/linux-6.14.4/Documentation/devicetree/bindings/perf/
Driscv,pmu.yaml1 # SPDX-License-Identifier: BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/perf/riscv,pmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V SBI PMU events
10 - Atish Patra <[email protected]>
13 The SBI PMU extension allows supervisor software to configure, start and
15 capabilities of performance analysis tools, such as perf, if the SBI PMU
20 Without the event to counter mappings, the SBI PMU extension cannot be used.
29 For information on the SBI specification see the section "Performance
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/linux-6.14.4/Documentation/devicetree/bindings/cpu/
Didle-states.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <[email protected]>
11 - Anup Patel <[email protected]>
15 1 - Introduction
18 ARM and RISC-V systems contain HW capable of managing power consumption
19 dynamically, where cores can be put in different low-power states (ranging
22 run-time, can be specified through device tree bindings representing the
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/linux-6.14.4/Documentation/devicetree/bindings/interrupt-controller/
Driscv,cpu-intc.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Hart-Level Interrupt Controller (HLIC)
10 RISC-V cores include Control Status Registers (CSRs) which are local to
11 each CPU core (HART in RISC-V terminology) and can be read or written by
16 The RISC-V supervisor ISA manual specifies three interrupt sources that are
19 cores. The timer interrupt comes from an architecturally mandated real-
20 time timer that is controlled via Supervisor Binary Interface (SBI) calls
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/linux-6.14.4/drivers/clocksource/
Dtimer-riscv.c1 // SPDX-License-Identifier: GPL-2.0
6 * All RISC-V systems have a timer attached to every hart. These timers can
7 * either be read from the "time" and "timeh" CSRs, and can use the SBI to
11 #define pr_fmt(fmt) "riscv-timer: " fmt
22 #include <linux/io-64-nonatomic-lo-hi.h>
26 #include <clocksource/timer-riscv.h>
29 #include <asm/sbi.h>
114 ce->cpumask = cpumask_of(cpu); in riscv_timer_starting_cpu()
115 ce->irq = riscv_clock_event_irq; in riscv_timer_starting_cpu()
117 ce->features |= CLOCK_EVT_FEAT_C3STOP; in riscv_timer_starting_cpu()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
60 bool "OMAP dual-mode timer driver" if ARCH_K3 || COMPILE_TEST
64 Enables the support for the TI dual-mode timer driver.
190 Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
213 32-bit free running decrementing counters.
248 bool "Integrator-AP timer driver" if COMPILE_TEST
251 Enables support for the Integrator-AP timer.
276 available on many OMAP-like platforms.
295 bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST
299 These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
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/linux-6.14.4/drivers/cpuidle/
Dcpuidle-riscv-sbi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * RISC-V SBI CPU idle driver.
9 #define pr_fmt(fmt) "cpuidle-riscv-sbi: " fmt
25 #include <asm/sbi.h>
53 data->available = true; in sbi_set_domain_state()
54 data->state = state; in sbi_set_domain_state()
61 return data->state; in sbi_get_domain_state()
68 data->available = false; in sbi_clear_domain_state()
75 return data->available; in sbi_is_domain_state_available()
96 u32 *states = data->states; in __sbi_enter_domain_idle_state()
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 # Branch profiling isn't noinstr-safe
7 ccflags-$(CONFIG_TRACE_BRANCH_PROFILING) += -DDISABLE_BRANCH_PROFILING
9 obj-y += cpuidle.o driver.o governor.o sysfs.o governors/
10 obj-$(CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED) += coupled.o
11 obj-$(CONFIG_DT_IDLE_STATES) += dt_idle_states.o
12 obj-$(CONFIG_DT_IDLE_GENPD) += dt_idle_genpd.o
13 obj-$(CONFIG_ARCH_HAS_CPU_RELAX) += poll_state.o
14 obj-$(CONFIG_HALTPOLL_CPUIDLE) += cpuidle-haltpoll.o
18 obj-$(CONFIG_ARM_MVEBU_V7_CPUIDLE) += cpuidle-mvebu-v7.o
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/linux-6.14.4/Documentation/devicetree/bindings/timer/
Driscv,timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/riscv,timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V timer
10 - Anup Patel <[email protected]>
13 RISC-V platforms always have a RISC-V timer device for the supervisor-mode
14 based on the time CSR defined by the RISC-V privileged specification. The
15 timer interrupts of this device are configured using the RISC-V SBI Time
16 extension or the RISC-V Sstc extension.
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/linux-6.14.4/arch/riscv/kernel/
Dsbi-ipi.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #define pr_fmt(fmt) "riscv: " fmt
14 #include <asm/sbi.h>
72 * via generic IPI-Mux in sbi_ipi_init()
75 "irqchip/sbi-ipi:starting", in sbi_ipi_init()
79 pr_info("providing IPIs using SBI IPI extension\n"); in sbi_ipi_init()
82 * Use the SBI remote fence extension to avoid in sbi_ipi_init()
Dparavirt.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #define pr_fmt(fmt) "riscv-pv: " fmt
15 #include <linux/percpu-defs.h>
23 #include <asm/sbi.h>
42 early_param("no-steal-acc", parse_no_stealacc);
50 pr_info("SBI STA extension detected\n"); in has_pv_steal_clock()
66 pr_warn("Failed to disable steal-time shmem"); in sbi_sta_steal_time_set_shmem()
68 pr_warn("Failed to set steal-time shmem"); in sbi_sta_steal_time_set_shmem()
102 sequence = READ_ONCE(st->sequence); in pv_time_steal_clock()
104 steal = READ_ONCE(st->steal); in pv_time_steal_clock()
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Dcpu.c1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <asm/sbi.h>
27 * Returns the hart ID of the given device tree node, or -ENODEV if the node
28 * isn't an enabled and valid RISC-V hart node.
37 return -ENODEV; in riscv_of_processor_hartid()
45 return -ENODEV; in riscv_of_processor_hartid()
54 if (!of_device_is_compatible(node, "riscv")) { in riscv_early_of_processor_hartid()
56 return -ENODEV; in riscv_early_of_processor_hartid()
62 return -ENODEV; in riscv_early_of_processor_hartid()
67 return -ENODEV; in riscv_early_of_processor_hartid()
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Dcpufeature.c1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <asm/text-patching.h>
27 #include <asm/sbi.h>
32 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
41 /* Per-cpu ISA extensions. */
47 * riscv_isa_extension_base() - Get base extension word
63 * __riscv_isa_extension_available() - Check whether given extension
87 pr_err("Zicbom detected in ISA string, disabling as no cbom-block-size found\n"); in riscv_ext_zicbom_validate()
88 return -EINVAL; in riscv_ext_zicbom_validate()
91 pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n"); in riscv_ext_zicbom_validate()
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Dsys_hwprobe.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * are supported by the hardware. See Documentation/arch/riscv/hwprobe.rst for
13 #include <asm/sbi.h>
25 u64 id = -1ULL; in hwprobe_arch_id()
32 switch (pair->key) { in hwprobe_arch_id()
50 * If there's a mismatch for the given set, return -1 in the in hwprobe_arch_id()
54 id = -1ULL; in hwprobe_arch_id()
59 pair->value = id; in hwprobe_arch_id()
68 pair->value = 0; in hwprobe_isa_ext0()
70 pair->value |= RISCV_HWPROBE_IMA_FD; in hwprobe_isa_ext0()
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/linux-6.14.4/include/linux/perf/
Driscv_pmu.h1 /* SPDX-License-Identifier: GPL-2.0 */
23 #define RISCV_OP_UNSUPP (-EOPNOTSUPP)
24 #define RISCV_PMU_SBI_PDEV_NAME "riscv-pmu-sbi"
25 #define RISCV_PMU_LEGACY_PDEV_NAME "riscv-pmu-legacy"
48 /* A shadow copy of the counter values to avoid clobbering during multiple SBI calls */
/linux-6.14.4/arch/riscv/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 # see Documentation/kbuild/kconfig-language.rst.
13 config RISCV config
66 # LLD >= 14: https://github.com/llvm/llvm-project/issues/50505
222 # -Zsanitizer=shadow-call-stack flag.
232 depends on $(cc-option,-fpatchable-function-entry=8)
235 def_bool $(cc-option,-fsanitize=shadow-call-stack)
236 …# https://github.com/riscv-non-isa/riscv-elf-psabi-doc/commit/a484e843e6eeb51f0cb7b8819e50da6d2444…
237 depends on $(ld-option,--no-relax-gp)
241 # https://github.com/llvm/llvm-project/commit/6611d58f5bbcbec77262d392e2923e1d680f6985
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/linux-6.14.4/drivers/perf/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
17 If compiled as a module, it will be called arm-cci.
20 bool "support CCI-400"
25 CCI-400 provides 4 independent event counters counting events related
29 bool "support CCI-500/CCI-550"
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
45 tristate "Arm CMN-600 PMU support"
48 Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
52 tristate "Arm NI-700 PMU support"
55 Support for PMU events monitoring on the Arm NI-700 Network-on-Chip
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Driscv_pmu_sbi.c1 // SPDX-License-Identifier: GPL-2.0
3 * RISC-V performance counter support.
11 #define pr_fmt(fmt) "riscv-pmu-sbi: " fmt
26 #include <asm/sbi.h>
62 PMU_FORMAT_ATTR(event, "config:0-47");
63 PMU_FORMAT_ATTR(firmware, "config:62-63");
90 * RISC-V doesn't have heterogeneous harts yet. This need to be part of
306 0, cmask, 0, edata->event_idx, 0, 0); in pmu_sbi_check_event()
312 edata->event_idx = -ENOENT; in pmu_sbi_check_event()
342 return (info->type == SBI_PMU_CTR_TYPE_FW) ? true : false; in pmu_sbi_ctr_is_fw()
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/linux-6.14.4/arch/riscv/mm/
Dcacheflush.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <asm/sbi.h>
35 * Performs an icache flush for the given MM context. RISC-V has no direct
39 * single-hart processes on a many-hart machine, ie 'make -j') we avoid the
52 mask = &mm->context.icache_stale_mask; in flush_icache_mm()
65 if (mm == current->active_mm && local) { in flush_icache_mm()
69 * and scheduling this MM context on that hart. Sending an SBI in flush_icache_mm()
91 if (!test_bit(PG_dcache_clean, &folio->flags)) { in flush_icache_pte()
93 set_bit(PG_dcache_clean, &folio->flags); in flush_icache_pte()
136 /* set block-size for cbom and/or cboz extension if available */ in riscv_init_cbo_blocksizes()
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/linux-6.14.4/arch/riscv/include/asm/
Dpgalloc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <asm/sbi.h>
16 #include <asm-generic/pgalloc.h>
19 * While riscv platforms with riscv_ipi_for_rfence as true require an IPI to
21 * SBI to perform TLB shootdown. To keep software pagetable walkers safe in this
23 * comment below 'ifdef CONFIG_MMU_GATHER_RCU_TABLE_FREE' in include/asm-generic/tlb.h
126 (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t)); in sync_kernel_mappings()
Dkvm_host.h1 /* SPDX-License-Identifier: GPL-2.0-only */
110 /* G-stage vmid */
113 /* G-stage page table */
265 /* SBI context */
287 /* SBI steal-time accounting */
296 * arrived in guest context. For riscv, any event that arrives while a vCPU is
/linux-6.14.4/Documentation/devicetree/bindings/riscv/
Dextensions.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/riscv/extensions.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <[email protected]>
11 - Palmer Dabbelt <[email protected]>
12 - Conor Dooley <[email protected]>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
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/linux-6.14.4/drivers/irqchip/
Dirq-riscv-intc.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2017-2018 SiFive
8 #define pr_fmt(fmt) "riscv-intc: " fmt
31 unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG; in riscv_intc_irq()
46 * On RISC-V systems local interrupts are masked or unmasked by writing
54 if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG) in riscv_intc_irq_mask()
55 csr_clear(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); in riscv_intc_irq_mask()
57 csr_clear(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_mask()
62 if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG) in riscv_intc_irq_unmask()
63 csr_set(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); in riscv_intc_irq_unmask()
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Dirq-thead-c900-aclint-sswi.c1 // SPDX-License-Identifier: GPL-2.0
6 #define pr_fmt(fmt) "thead-c900-aclint-sswi: " fmt
21 #include <asm/sbi.h>
83 return -EINVAL; in thead_aclint_sswi_parse_irq()
96 return -ENOTSUPP; in thead_aclint_sswi_parse_irq()
114 /* If it is T-HEAD CPU, check whether SSWI is enabled */ in thead_aclint_sswi_probe()
117 return -ENOTSUPP; in thead_aclint_sswi_probe()
120 return -EINVAL; in thead_aclint_sswi_probe()
124 return -ENOMEM; in thead_aclint_sswi_probe()
135 /* Find riscv intc domain and create IPI irq mapping */ in thead_aclint_sswi_probe()
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/linux-6.14.4/Documentation/arch/riscv/
Dboot.rst1 .. SPDX-License-Identifier: GPL-2.0
4 RISC-V Kernel Boot Requirements and Constraints
10 This document describes what the RISC-V kernel expects from bootloaders and
16 Pre-kernel Requirements and Constraints
19 The RISC-V kernel expects the following of bootloaders and platform firmware:
22 --------------
24 The RISC-V kernel expects:
30 ---------
32 The RISC-V kernel expects:
37 -------------------------------------
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/linux-6.14.4/drivers/tty/serial/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 obj-$(CONFIG_SERIAL_CORE) += serial_base.o
7 serial_base-y := serial_core.o serial_base_bus.o serial_ctrl.o serial_port.o
9 obj-$(CONFIG_SERIAL_EARLYCON) += earlycon.o
10 obj-$(CONFIG_SERIAL_EARLYCON_SEMIHOST) += earlycon-semihost.o
11 obj-$(CONFIG_SERIAL_EARLYCON_RISCV_SBI) += earlycon-riscv-sbi.o
16 obj-$(CONFIG_SERIAL_SUNCORE) += suncore.o
17 obj-$(CONFIG_SERIAL_SUNHV) += sunhv.o
18 obj-$(CONFIG_SERIAL_SUNZILOG) += sunzilog.o
19 obj-$(CONFIG_SERIAL_SUNSU) += sunsu.o
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