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/linux-6.14.4/Documentation/devicetree/bindings/iommu/
Driscv,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iommu/riscv,iommu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V IOMMU Architecture Implementation
10 - Tomasz Jeznach <[email protected]>
13 The RISC-V IOMMU provides memory address translation and isolation for
14 input and output devices, supporting per-device translation context,
17 It supports identical translation table format to the RISC-V address
19 Hardware uses in-memory command and fault reporting queues with wired
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/linux-6.14.4/drivers/iommu/riscv/
Diommu-platform.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * RISC-V IOMMU as a platform device
5 * Copyright © 2023 FORTH-ICS/CARV
6 * Copyright © 2023-2024 Rivos Inc.
19 #include "iommu-bits.h"
20 #include "iommu.h"
25 struct riscv_iommu_device *iommu = dev_get_drvdata(dev); in riscv_iommu_write_msi_msg() local
26 u16 idx = desc->msi_index; in riscv_iommu_write_msi_msg()
29 addr = ((u64)msg->address_hi << 32) | msg->address_lo; in riscv_iommu_write_msi_msg()
33 "uh oh, the IOMMU can't send MSIs to 0x%llx, sending to 0x%llx instead\n", in riscv_iommu_write_msi_msg()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 # RISC-V IOMMU support
5 bool "RISC-V IOMMU Support"
6 depends on RISCV && 64BIT
10 Support for implementations of the RISC-V IOMMU architecture that
11 complements the RISC-V MMU capabilities, providing similar address
14 Say Y here if your SoC includes an IOMMU device implementing
15 the RISC-V IOMMU architecture.
20 Support for the PCIe implementation of RISC-V IOMMU architecture.
Diommu-pci.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright © 2022-2024 Rivos Inc.
5 * Copyright © 2023 FORTH-ICS/CARV
7 * RISCV IOMMU as a PCIe device
16 #include <linux/iommu.h>
20 #include "iommu-bits.h"
21 #include "iommu.h"
23 /* QEMU RISC-V IOMMU implementation */
35 struct device *dev = &pdev->dev; in riscv_iommu_pci_probe()
36 struct riscv_iommu_device *iommu; in riscv_iommu_pci_probe() local
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Diommu-bits.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2022-2024 Rivos Inc.
4 * Copyright © 2023 FORTH-ICS/CARV
5 * Copyright © 2023 RISC-V IOMMU Task Group
7 * RISC-V IOMMU - Register Layout and Data Structures.
9 * Based on the 'RISC-V IOMMU Architecture Specification', Version 1.0
10 * Published at https://github.com/riscv-non-isa/riscv-iommu
39 /* 5.3 IOMMU Capabilities (64bits) */
67 * enum riscv_iommu_igs_settings - Interrupt Generation Support Settings
68 * @RISCV_IOMMU_CAPABILITIES_IGS_MSI: IOMMU supports only MSI generation
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Diommu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * IOMMU API for RISC-V IOMMU implementations.
5 * Copyright © 2022-2024 Rivos Inc.
6 * Copyright © 2023 FORTH-ICS/CARV
13 #define pr_fmt(fmt) "riscv-iommu: " fmt
18 #include <linux/iommu.h>
23 #include "../iommu-pages.h"
24 #include "iommu-bits.h"
25 #include "iommu.h"
37 /* RISC-V IOMMU PPN <> PHYS address conversions, PHYS <=> PPN[53:10] */
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/linux-6.14.4/drivers/iommu/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-y += amd/ intel/ arm/ iommufd/ riscv/
3 obj-$(CONFIG_IOMMU_API) += iommu.o
4 obj-$(CONFIG_IOMMU_API) += iommu-traces.o
5 obj-$(CONFIG_IOMMU_API) += iommu-sysfs.o
6 obj-$(CONFIG_IOMMU_DEBUGFS) += iommu-debugfs.o
7 obj-$(CONFIG_IOMMU_DMA) += dma-iommu.o
8 obj-$(CONFIG_IOMMU_IO_PGTABLE) += io-pgtable.o
9 obj-$(CONFIG_IOMMU_IO_PGTABLE_ARMV7S) += io-pgtable-arm-v7s.o
10 obj-$(CONFIG_IOMMU_IO_PGTABLE_LPAE) += io-pgtable-arm.o
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 # The IOVA library may also be used by non-IOMMU_API users
15 bool "IOMMU Hardware Support"
26 menu "Generic IOMMU Pagetable Support"
40 sizes at both stage-1 and stage-2, as well as address spaces
41 up to 48-bits in size.
47 Enable self-tests for LPAE page table allocator. This performs
48 a series of page-table consistency checks during boot.
57 Enable support for the ARM Short-descriptor pagetable format.
58 This supports 32-bit virtual and physical addresses mapped using
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/linux-6.14.4/drivers/gpu/drm/tegra/
Dnvdec.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015-2022, NVIDIA Corporation.
8 #include <linux/dma-mapping.h>
10 #include <linux/iommu.h>
22 #include "riscv.h"
50 /* RISC-V specific data */
51 struct tegra_drm_riscv riscv; member
63 writel(value, nvdec->regs + offset); in nvdec_writel()
71 if (nvdec->config->supports_sid && tegra_dev_iommu_get_stream_id(nvdec->dev, &stream_id)) { in nvdec_boot_falcon()
81 err = falcon_boot(&nvdec->falcon); in nvdec_boot_falcon()
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/linux-6.14.4/drivers/firmware/efi/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
42 resource, and set aside for direct-access (device-dax) by
45 device-dax kmem facility. Say N to have the kernel treat this
83 memory before executing it. For compatibility with non-EFI loaders,
90 depends on EFI_GENERIC_STUB && !RISCV && !LOONGARCH
129 bool "Add support for Quark capsules with non-standard headers"
202 kernel. System firmware may configure the IOMMU to prevent malicious
204 firmware can't guarantee that the OS is IOMMU-aware, it will tear
205 down IOMMU configuration when ExitBootServices() is called. This
207 damage before Linux configures the IOMMU again.
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/linux-6.14.4/Documentation/admin-guide/
Dkernel-parameters.txt16 force -- enable ACPI if default was off
17 on -- enable ACPI but allow fallback to DT [arm64,riscv64]
18 off -- disable ACPI if default was on
19 noirq -- do not use ACPI for IRQ routing
20 strict -- Be less tolerant of platforms that are not
22 rsdt -- prefer RSDT over (default) XSDT
23 copy_dsdt -- copy DSDT to memory
24 nocmcff -- Disable firmware first mode for corrected
28 nospcr -- disable console in ACPI SPCR table as
45 If set to vendor, prefer vendor-specific driver
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/linux-6.14.4/tools/testing/selftests/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
4 TARGETS += amd-pstate
15 TARGETS += cpu-hotplug
19 TARGETS += dmabuf-heaps
20 TARGETS += drivers/dma-buf
45 TARGETS += iommu
58 TARGETS += memory-hotplug
89 TARGETS += riscv
105 TARGETS += tc-testing
126 TARGETS_HOTPLUG = cpu-hotplug
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/linux-6.14.4/
DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-[email protected]
88 F: drivers/scsi/3w-*
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/linux-6.14.4/drivers/clk/sunxi-ng/
Dccu-sun20i-d1.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
26 #include "ccu-sun20i-d1.h"
43 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-cpux", osc24M,
59 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-ddr0", osc24M,
73 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-periph0-4x", osc24M,
82 static SUNXI_CCU_M_HWS(pll_periph0_2x_clk, "pll-periph0-2x",
84 static SUNXI_CCU_M_HWS(pll_periph0_800M_clk, "pll-periph0-800M",
90 static CLK_FIXED_FACTOR_HWS(pll_periph0_clk, "pll-periph0",
94 static CLK_FIXED_FACTOR_HWS(pll_periph0_div3_clk, "pll-periph0-div3",
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/linux-6.14.4/arch/riscv/kvm/
Daia_imsic.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/irqchip/riscv-imsic.h>
44 * 1) Hardware: IMSIC VS-file (vsfile_cpu >= 0)
45 * 2) Software: IMSIC SW-file (vsfile_cpu < 0)
48 /* IMSIC VS-file */
55 /* IMSIC SW-file */
243 imsic_mrif_atomic_rmw(__mrif, __ptr, __new_val, -1UL)
253 &mrif->eithreshold); in imsic_mrif_topei()
258 eix = &mrif->eix[ei]; in imsic_mrif_topei()
259 eipend[0] = imsic_mrif_atomic_read(mrif, &eix->eie[0]) & in imsic_mrif_topei()
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/linux-6.14.4/Documentation/virt/kvm/
Dapi.rst1 .. SPDX-License-Identifier: GPL-2.0
4 The Definitive KVM (Kernel-based Virtual Machine) API Documentation
24 - System ioctls: These query and set global attributes which affect the
28 - VM ioctls: These query and set attributes that affect an entire virtual
35 - vcpu ioctls: These query and set attributes that control the operation
43 - device ioctls: These query and set attributes that control the operation
92 facility that allows backward-compatible extensions to the API to be
133 -----------------------
150 -----------------
189 address used by the VM. The IPA_Bits is encoded in bits[7-0] of the
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