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/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.cpp1 //===-- R600InstrInfo.cpp - R600 Instruction Information ------------------===//
10 /// R600 Implementation of TargetInstrInfo.
17 #include "R600.h"
45 if ((R600::R600_Reg128RegClass.contains(DestReg) || in copyPhysReg()
46 R600::R600_Reg128VerticalRegClass.contains(DestReg)) && in copyPhysReg()
47 (R600::R600_Reg128RegClass.contains(SrcReg) || in copyPhysReg()
48 R600::R600_Reg128VerticalRegClass.contains(SrcReg))) { in copyPhysReg()
50 } else if((R600::R600_Reg64RegClass.contains(DestReg) || in copyPhysReg()
51 R600::R600_Reg64VerticalRegClass.contains(DestReg)) && in copyPhysReg()
52 (R600::R600_Reg64RegClass.contains(SrcReg) || in copyPhysReg()
[all …]
H A DR600RegisterInfo.cpp1 //===-- R600RegisterInfo.cpp - R600 Register Information ------------------===//
10 /// R600 implementation of the TargetRegisterInfo class.
26 R600::sub0, R600::sub1, R600::sub2, R600::sub3, in getSubRegFromChannel()
27 R600::sub4, R600::sub5, R600::sub6, R600::sub7, in getSubRegFromChannel()
28 R600::sub8, R600::sub9, R600::sub10, R600::sub11, in getSubRegFromChannel()
29 R600::sub12, R600::sub13, R600::sub14, R600::sub15 in getSubRegFromChannel()
42 reserveRegisterTuples(Reserved, R600::ZERO); in getReservedRegs()
43 reserveRegisterTuples(Reserved, R600::HALF); in getReservedRegs()
44 reserveRegisterTuples(Reserved, R600::ONE); in getReservedRegs()
45 reserveRegisterTuples(Reserved, R600::ONE_INT); in getReservedRegs()
[all …]
H A DR600ControlFlowFinalizer.cpp16 #include "R600.h"
67 if (Opcode == R600::CF_ALU_PUSH_BEFORE && ST->hasCaymanISA() && in requiresWorkAroundForInst()
76 case R600::CF_ALU_PUSH_BEFORE: in requiresWorkAroundForInst()
77 case R600::CF_ALU_ELSE_AFTER: in requiresWorkAroundForInst()
78 case R600::CF_ALU_BREAK: in requiresWorkAroundForInst()
79 case R600::CF_ALU_CONTINUE: in requiresWorkAroundForInst()
140 case R600::CF_PUSH_EG: in pushBranch()
141 case R600::CF_ALU_PUSH_BEFORE: in pushBranch()
212 case R600::KILL: in IsTrivialInst()
213 case R600::RETURN: in IsTrivialInst()
[all …]
H A DR600ISelLowering.cpp1 //===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===//
10 /// Custom DAG lowering for R600
33 addRegisterClass(MVT::f32, &R600::R600_Reg32RegClass); in R600TargetLowering()
34 addRegisterClass(MVT::i32, &R600::R600_Reg32RegClass); in R600TargetLowering()
35 addRegisterClass(MVT::v2f32, &R600::R600_Reg64RegClass); in R600TargetLowering()
36 addRegisterClass(MVT::v2i32, &R600::R600_Reg64RegClass); in R600TargetLowering()
37 addRegisterClass(MVT::v4f32, &R600::R600_Reg128RegClass); in R600TargetLowering()
38 addRegisterClass(MVT::v4i32, &R600::R600_Reg128RegClass); in R600TargetLowering()
179 // need it for R600. in R600TargetLowering()
208 return std::next(I)->getOpcode() == R600::RETURN; in isEOP()
[all …]
H A DR600ExpandSpecialInstrs.cpp17 #include "R600.h"
25 #define DEBUG_TYPE "r600-expand-special-instrs"
44 return "R600 Expand special instructions pass"; in getPassName()
51 "R600 Expand Special Instrs", false, false)
86 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst); in runOnMachineFunction()
90 DstOp.getReg(), R600::OQAP); in runOnMachineFunction()
91 DstOp.setReg(R600::OQAP); in runOnMachineFunction()
93 R600::OpName::pred_sel); in runOnMachineFunction()
95 R600::OpName::pred_sel); in runOnMachineFunction()
104 case R600::PRED_X: { in runOnMachineFunction()
[all …]
H A DR600MachineScheduler.cpp1 //===-- R600MachineScheduler.cpp - R600 Scheduler Interface -*- C++ -*-----===//
10 /// R600 Machine Scheduler interface
157 if (MO.isReg() && MO.getReg() == R600::ALU_LITERAL_X) in schedNode()
176 if (MI->getOpcode() != R600::COPY) in isPhysicalRegCopy()
219 case R600::PRED_X: in getAluKind()
221 case R600::INTERP_PAIR_XY: in getAluKind()
222 case R600::INTERP_PAIR_ZW: in getAluKind()
223 case R600::INTERP_VEC_LOAD: in getAluKind()
224 case R600::DOT_4: in getAluKind()
226 case R600::COPY: in getAluKind()
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/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.cpp1 //===-- R600InstrInfo.cpp - R600 Instruction Information ------------------===//
10 /// R600 Implementation of TargetInstrInfo.
66 if ((R600::R600_Reg128RegClass.contains(DestReg) || in copyPhysReg()
67 R600::R600_Reg128VerticalRegClass.contains(DestReg)) && in copyPhysReg()
68 (R600::R600_Reg128RegClass.contains(SrcReg) || in copyPhysReg()
69 R600::R600_Reg128VerticalRegClass.contains(SrcReg))) { in copyPhysReg()
71 } else if((R600::R600_Reg64RegClass.contains(DestReg) || in copyPhysReg()
72 R600::R600_Reg64VerticalRegClass.contains(DestReg)) && in copyPhysReg()
73 (R600::R600_Reg64RegClass.contains(SrcReg) || in copyPhysReg()
74 R600::R600_Reg64VerticalRegClass.contains(SrcReg))) { in copyPhysReg()
[all …]
H A DR600ControlFlowFinalizer.cpp96 if (Opcode == R600::CF_ALU_PUSH_BEFORE && ST->hasCaymanISA() && in requiresWorkAroundForInst()
105 case R600::CF_ALU_PUSH_BEFORE: in requiresWorkAroundForInst()
106 case R600::CF_ALU_ELSE_AFTER: in requiresWorkAroundForInst()
107 case R600::CF_ALU_BREAK: in requiresWorkAroundForInst()
108 case R600::CF_ALU_CONTINUE: in requiresWorkAroundForInst()
170 case R600::CF_PUSH_EG: in pushBranch()
171 case R600::CF_ALU_PUSH_BEFORE: in pushBranch()
242 case R600::KILL: in IsTrivialInst()
243 case R600::RETURN: in IsTrivialInst()
255 Opcode = isEg ? R600::CF_TC_EG : R600::CF_TC_R600; in getHWInstrDesc()
[all …]
H A DR600ISelLowering.cpp1 //===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===//
10 /// Custom DAG lowering for R600
59 addRegisterClass(MVT::f32, &R600::R600_Reg32RegClass); in R600TargetLowering()
60 addRegisterClass(MVT::i32, &R600::R600_Reg32RegClass); in R600TargetLowering()
61 addRegisterClass(MVT::v2f32, &R600::R600_Reg64RegClass); in R600TargetLowering()
62 addRegisterClass(MVT::v2i32, &R600::R600_Reg64RegClass); in R600TargetLowering()
63 addRegisterClass(MVT::v4f32, &R600::R600_Reg128RegClass); in R600TargetLowering()
64 addRegisterClass(MVT::v4i32, &R600::R600_Reg128RegClass); in R600TargetLowering()
252 // need it for R600. in R600TargetLowering()
288 return std::next(I)->getOpcode() == R600::RETURN; in isEOP()
[all …]
H A DR600ExpandSpecialInstrs.cpp35 #define DEBUG_TYPE "r600-expand-special-instrs"
54 return "R600 Expand special instructions pass"; in getPassName()
61 "R600 Expand Special Instrs", false, false)
98 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst); in runOnMachineFunction()
102 DstOp.getReg(), R600::OQAP); in runOnMachineFunction()
103 DstOp.setReg(R600::OQAP); in runOnMachineFunction()
105 R600::OpName::pred_sel); in runOnMachineFunction()
107 R600::OpName::pred_sel); in runOnMachineFunction()
116 case R600::PRED_X: { in runOnMachineFunction()
124 R600::ZERO); // src1 in runOnMachineFunction()
[all …]
H A DR600RegisterInfo.cpp1 //===-- R600RegisterInfo.cpp - R600 Register Information ------------------===//
10 /// R600 implementation of the TargetRegisterInfo class.
37 reserveRegisterTuples(Reserved, R600::ZERO); in getReservedRegs()
38 reserveRegisterTuples(Reserved, R600::HALF); in getReservedRegs()
39 reserveRegisterTuples(Reserved, R600::ONE); in getReservedRegs()
40 reserveRegisterTuples(Reserved, R600::ONE_INT); in getReservedRegs()
41 reserveRegisterTuples(Reserved, R600::NEG_HALF); in getReservedRegs()
42 reserveRegisterTuples(Reserved, R600::NEG_ONE); in getReservedRegs()
43 reserveRegisterTuples(Reserved, R600::PV_X); in getReservedRegs()
44 reserveRegisterTuples(Reserved, R600::ALU_LITERAL_X); in getReservedRegs()
[all …]
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567/include/llvm/IR/
DIntrinsicsR600.h16 r600_cube = 9848, // llvm.r600.cube
17 r600_ddx, // llvm.r600.ddx
18 r600_ddy, // llvm.r600.ddy
19 r600_dot4, // llvm.r600.dot4
20 r600_group_barrier, // llvm.r600.group.barrier
21 r600_implicitarg_ptr, // llvm.r600.implicitarg.ptr
22 r600_kill, // llvm.r600.kill
23 r600_rat_store_typed, // llvm.r600.rat.store.typed
24 r600_read_global_size_x, // llvm.r600.read.global.size.x
25 r600_read_global_size_y, // llvm.r600.read.global.size.y
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/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/configs/common/include/llvm/IR/
H A DIntrinsicsR600.h16 r600_cube = 7729, // llvm.r600.cube
17 r600_ddx, // llvm.r600.ddx
18 r600_ddy, // llvm.r600.ddy
19 r600_dot4, // llvm.r600.dot4
20 r600_group_barrier, // llvm.r600.group.barrier
21 r600_implicitarg_ptr, // llvm.r600.implicitarg.ptr
22 r600_kill, // llvm.r600.kill
23 r600_rat_store_typed, // llvm.r600.rat.store.typed
24 r600_read_global_size_x, // llvm.r600.read.global.size.x
25 r600_read_global_size_y, // llvm.r600.read.global.size.y
[all …]
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r536225/include/llvm/IR/
DIntrinsicsR600.h16 r600_cube = 9871, // llvm.r600.cube
17 r600_ddx, // llvm.r600.ddx
18 r600_ddy, // llvm.r600.ddy
19 r600_dot4, // llvm.r600.dot4
20 r600_group_barrier, // llvm.r600.group.barrier
21 r600_implicitarg_ptr, // llvm.r600.implicitarg.ptr
22 r600_kill, // llvm.r600.kill
23 r600_rat_store_typed, // llvm.r600.rat.store.typed
24 r600_read_global_size_x, // llvm.r600.read.global.size.x
25 r600_read_global_size_y, // llvm.r600.read.global.size.y
[all …]
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r522817/include/llvm/IR/
DIntrinsicsR600.h16 r600_cube = 9705, // llvm.r600.cube
17 r600_ddx, // llvm.r600.ddx
18 r600_ddy, // llvm.r600.ddy
19 r600_dot4, // llvm.r600.dot4
20 r600_group_barrier, // llvm.r600.group.barrier
21 r600_implicitarg_ptr, // llvm.r600.implicitarg.ptr
22 r600_kill, // llvm.r600.kill
23 r600_rat_store_typed, // llvm.r600.rat.store.typed
24 r600_read_global_size_x, // llvm.r600.read.global.size.x
25 r600_read_global_size_y, // llvm.r600.read.global.size.y
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/
H A DIntrinsicsR600.h16 r600_cube = 6004, // llvm.r600.cube
17 r600_ddx, // llvm.r600.ddx
18 r600_ddy, // llvm.r600.ddy
19 r600_dot4, // llvm.r600.dot4
20 r600_group_barrier, // llvm.r600.group.barrier
21 r600_implicitarg_ptr, // llvm.r600.implicitarg.ptr
22 r600_kill, // llvm.r600.kill
23 r600_rat_store_typed, // llvm.r600.rat.store.typed
24 r600_read_global_size_x, // llvm.r600.read.global.size.x
25 r600_read_global_size_y, // llvm.r600.read.global.size.y
[all …]
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567b/include/llvm/IR/
DIntrinsicsR600.h16 r600_cube = 9848, // llvm.r600.cube
17 r600_ddx, // llvm.r600.ddx
18 r600_ddy, // llvm.r600.ddy
19 r600_dot4, // llvm.r600.dot4
20 r600_group_barrier, // llvm.r600.group.barrier
21 r600_implicitarg_ptr, // llvm.r600.implicitarg.ptr
22 r600_kill, // llvm.r600.kill
23 r600_rat_store_typed, // llvm.r600.rat.store.typed
24 r600_read_global_size_x, // llvm.r600.read.global.size.x
25 r600_read_global_size_y, // llvm.r600.read.global.size.y
[all …]
/aosp_15_r20/external/llvm/test/CodeGen/AMDGPU/
H A Dannotate-kernel-features.ll3 declare i32 @llvm.r600.read.tgid.x() #0
4 declare i32 @llvm.r600.read.tgid.y() #0
5 declare i32 @llvm.r600.read.tgid.z() #0
7 declare i32 @llvm.r600.read.tidig.x() #0
8 declare i32 @llvm.r600.read.tidig.y() #0
9 declare i32 @llvm.r600.read.tidig.z() #0
11 declare i32 @llvm.r600.read.local.size.x() #0
12 declare i32 @llvm.r600.read.local.size.y() #0
13 declare i32 @llvm.r600.read.local.size.z() #0
17 %val = call i32 @llvm.r600.read.tgid.x()
[all …]
H A Dsetcc.ll2 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600 --check-prefix=FUNC %s
4 declare i32 @llvm.r600.read.tidig.x() nounwind readnone
7 ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW]}}, KC0[3].X, KC0[3].Z
8 ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW]}}, KC0[2].W, KC0[3].Y
18 ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
19 ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
20 ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
21 ; R600-DAG: SETE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
38 ; R600: SETE_DX10
49 ; R600: SETGT_DX10
[all …]
H A Dfdiv.ll6 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
15 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W
16 ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, PS
38 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W
39 ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, PS
54 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W
55 ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, PS
70 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Z
71 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Y
72 ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, PS
[all …]
H A Dwrong-transalu-pos-fix.ll1 ; RUN: llc -march=r600 -mcpu=redwood -mtriple=r600-- < %s | FileCheck %s
9 %x.i = tail call i32 @llvm.r600.read.global.size.x() #1
10 %y.i18 = tail call i32 @llvm.r600.read.global.size.y() #1
12 %z.i17 = tail call i32 @llvm.r600.read.global.size.z() #1
14 %x.i.i = tail call i32 @llvm.r600.read.tgid.x() #1
15 %x.i12.i = tail call i32 @llvm.r600.read.local.size.x() #1
17 %x.i4.i = tail call i32 @llvm.r600.read.tidig.x() #1
20 %y.i.i = tail call i32 @llvm.r600.read.tgid.y() #1
21 %y.i14.i = tail call i32 @llvm.r600.read.local.size.y() #1
23 %y.i6.i = tail call i32 @llvm.r600.read.tidig.y() #1
[all …]
H A Dfetch-limits.r700+.ll1 ; RUN: llc < %s -march=r600 -mcpu=rv710 | FileCheck %s
2 ; RUN: llc < %s -march=r600 -mcpu=rv730 | FileCheck %s
3 ; RUN: llc < %s -march=r600 -mcpu=rv770 | FileCheck %s
4 ; RUN: llc < %s -march=r600 -mcpu=cedar | FileCheck %s
5 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
6 ; RUN: llc < %s -march=r600 -mcpu=sumo | FileCheck %s
7 ; RUN: llc < %s -march=r600 -mcpu=juniper | FileCheck %s
8 ; RUN: llc < %s -march=r600 -mcpu=cypress | FileCheck %s
9 ; RUN: llc < %s -march=r600 -mcpu=barts | FileCheck %s
10 ; RUN: llc < %s -march=r600 -mcpu=turks | FileCheck %s
[all …]
H A Duint_to_fp.ll3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
8 ; R600: UINT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[2].Z
18 ; R600: INT_TO_FLT
20 %tid = call i32 @llvm.r600.read.tidig.x()
33 ; R600-DAG: UINT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[2].W
34 ; R600-DAG: UINT_TO_FLT * T{{[0-9]+\.[XYZW]}}, KC0[3].X
48 ; R600: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
49 ; R600: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
50 ; R600: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
51 ; R600: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
[all …]
/aosp_15_r20/external/mesa3d/src/gallium/drivers/r600/sfn/
H A Dsfn_nir.cpp33 namespace r600 { namespace
269 * with "iadd bufid, 1", bot on r600 we can put that constant
325 } // namespace r600
413 bool result = r600::LowerClipvertexWrite(noutputs, so_info).run(sh); in r600_lower_clipvertex_to_clipdist()
449 using r600::r600_lower_fs_out_to_vector;
450 using r600::r600_lower_scratch_addresses;
451 using r600::r600_lower_ubo_to_align16;
614 return r600::OptIndirectUBOLoads().run(shader); in r600_opt_indirect_fbo_loads()
740 r600::sort_uniforms(sh); in r600_lower_and_optimize_nir()
755 r600::sort_fsoutput(sh); in r600_lower_and_optimize_nir()
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/aosp_15_r20/external/clang/test/Driver/
H A Dr600-mcpu.cl3 // RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=r600 %s -o - 2>&1 | FileCheck --check-pr…
4 // RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=rv630 %s -o - 2>&1 | FileCheck --check-p…
5 // RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=rv635 %s -o - 2>&1 | FileCheck --check-p…
6 // RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=rv610 %s -o - 2>&1 | FileCheck --check-p…
7 // RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=rv620 %s -o - 2>&1 | FileCheck --check-p…
8 // RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=rs780 %s -o - 2>&1 | FileCheck --check-p…
9 // RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=rs880 %s -o - 2>&1 | FileCheck --check-p…
10 // RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=rv670 %s -o - 2>&1 | FileCheck --check-p…
11 // RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=rv710 %s -o - 2>&1 | FileCheck --check-p…
12 // RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=rv730 %s -o - 2>&1 | FileCheck --check-p…
[all …]

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