Searched full:queue0 (Results 1 – 25 of 39) sorted by relevance
12
146 queue = pio->queue0; in parse_cookie()402 b43legacy_destroy_pioqueue(pio->queue0); in b43legacy_pio_free()403 pio->queue0 = NULL; in b43legacy_pio_free()415 pio->queue0 = queue; in b43legacy_pio_init()447 b43legacy_destroy_pioqueue(pio->queue0); in b43legacy_pio_init()448 pio->queue0 = NULL; in b43legacy_pio_init()657 pio->queue0->tx_frozen = 1; in b43legacy_pio_freeze_txqueues()669 pio->queue0->tx_frozen = 0; in b43legacy_pio_thaw_txqueues()673 if (!list_empty(&pio->queue0->txqueue)) in b43legacy_pio_thaw_txqueues()674 tasklet_schedule(&pio->queue0->txtask); in b43legacy_pio_thaw_txqueues()
538 struct b43legacy_pioqueue *queue0; member
76 queue0 {};82 queue0 {};
885 queue0 {};891 queue0 {};
71 queue0 {87 queue0 {
674 queue0 {684 queue0 {
37 - const: qdma-queue0125 interrupt-names = "qdma-error", "qdma-queue0", "qdma-queue1";
200 queue0 {230 queue0 {277 queue0 {307 queue0 {
386 queue0 {416 queue0 {455 queue0 {485 queue0 {
232 queue0 {262 queue0 {
350 queue0 {362 queue0 {
75 queue0 {109 queue0 {
323 queue0 {353 queue0 {
217 queue0 {246 queue0 {
253 queue0 {287 queue0 {
321 queue0 {};326 queue0 {};
8 * queue0, 2 from queue1, 4 from queue2 and so on.55 } queue0 SEC(".maps"),68 [0] = &queue0,
295 queue0 {};300 queue0 {};
367 queue0 {};373 queue0 {};
1168 queue0 {};1173 queue0 {};1215 queue0 {};1220 queue0 {};
659 queue0 {};664 queue0 {};
567 #define AR5K_QCU_TXDP_BASE 0x0800 /* Register Address - Queue0 TXDP */587 #define AR5K_QCU_CBRCFG_BASE 0x08c0 /* Register Address - Queue0 CBRCFG */597 #define AR5K_QCU_RDYTIMECFG_BASE 0x0900 /* Register Address - Queue0 RDYTIMECFG */618 #define AR5K_QCU_MISC_BASE 0x09c0 /* Register Address -Queue0 MISC */640 #define AR5K_QCU_STS_BASE 0x0a00 /* Register Address - Queue0 STS */685 #define AR5K_DCU_QCUMASK_BASE 0x1000 /* Register Address -Queue0 DCU_QCUMASK */692 #define AR5K_DCU_LCL_IFS_BASE 0x1040 /* Register Address -Queue0 DCU_LCL_IFS */706 #define AR5K_DCU_RETRY_LMT_BASE 0x1080 /* Register Address -Queue0 DCU_RETRY_LMT */718 #define AR5K_DCU_CHAN_TIME_BASE 0x10c0 /* Register Address -Queue0 DCU_CHAN_TIME */736 #define AR5K_DCU_MISC_BASE 0x1100 /* Register Address -Queue0 DCU_MISC */
658 queue0 {};663 queue0 {};
703 queue0 {713 queue0 {
892 /* Enable TSO on queue0 and enable TBS on rest of the queues */ in qcom_ethqos_probe()