Searched full:ptw (Results 1 – 23 of 23) sorted by relevance
| /linux-6.14.4/arch/sh/include/cpu-sh4/cpu/ |
| D | sh7724.h | 97 /* PTW */
134 /* ATAPI (PTA/PTB/PTK/PTR/PTS/PTW) */
249 /* SDHI1 (PTW) */
253 /* MMC (PTW/PTX)*/
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| D | sh7757.h | 94 /* PTW */
232 /* PTW (mobule: LBSC, EVC, SCIF) */
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| D | sh7722.h | 89 /* PTW */
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| D | sh7723.h | 95 /* PTW */
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| /linux-6.14.4/Documentation/devicetree/bindings/iommu/ |
| D | arm,smmu.yaml | 302 the smmu ptw
327 - description: bus clock required for the smmu ptw
344 the smmu ptw
371 - description: bus clock required for the smmu ptw
391 the smmu ptw
447 the smmu ptw
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| /linux-6.14.4/tools/perf/scripts/python/bin/ |
| D | intel-pt-events-record | 8 echo "Options must include the Intel PT event e.g. -e intel_pt/pwr_evt,ptw/"
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| /linux-6.14.4/arch/arm64/kvm/ |
| D | at.c | 56 bool ptw; member
63 static void fail_s1_walk(struct s1_walk_result *wr, u8 fst, bool ptw, bool s2) in fail_s1_walk() argument
66 wr->ptw = ptw; in fail_s1_walk()
790 par |= wr->ptw ? SYS_PAR_EL1_PTW : 0; in compute_par_s1()
1322 * know for sure that the PTW was able to walk the S1 tables and in __kvm_at_s1e01()
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| /linux-6.14.4/arch/csky/include/asm/ |
| D | barrier.h | 80 * Using three sync.is to prevent speculative PTW
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| /linux-6.14.4/arch/loongarch/kernel/ |
| D | proc.c | 70 if (cpu_has_ptw) seq_printf(m, " ptw"); in show_cpuinfo()
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| /linux-6.14.4/drivers/usb/chipidea/ |
| D | bits.h | 77 /* PTS and PTW for non lpm version only */
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| /linux-6.14.4/arch/sh/boards/ |
| D | board-sh7757lcr.c | 446 /* SCIF3/4 (PTJ, PTW) */ in sh7757lcr_devices_setup()
529 /* EVC (PTV, PTW) */ in sh7757lcr_devices_setup()
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| /linux-6.14.4/drivers/pinctrl/renesas/ |
| D | pfc-sh7757.c | 461 /* PTW (mobule: LBSC, EVC, SCIF) */
691 /* PTW GPIO */
1012 /* PTW FN */
1290 /* PTW */
1623 /* PTW (mobule: LBSC, EVC, SCIF) */
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| D | pfc-sh7724.c | 483 /*PTW*/
712 /* PTW GPIO */
1075 /* PTW FN */
1332 /* PTW */
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| D | pfc-sh7723.c | 520 /* PTW GPIO */
862 /* PTW FN */
1093 /* PTW */
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| D | pfc-sh7722.c | 428 /* PTW */
919 /* PTW */
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| /linux-6.14.4/arch/arm64/include/asm/ |
| D | kvm_arm.h | 93 * PTW: Take a stage2 fault if a stage1 walk steps in device memory
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| /linux-6.14.4/drivers/iommu/ |
| D | exynos-iommu.c | 216 "PTW",
224 "PTW",
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| D | sun50i-iommu.c | 331 dev_warn(iommu->dev, "PTW cache invalidation timed out!\n"); in sun50i_iommu_zap_ptw_cache()
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| /linux-6.14.4/arch/x86/events/intel/ |
| D | pt.c | 114 PMU_FORMAT_ATTR(ptw, "config:12" );
376 /* FUPonPTW without PTW doesn't make sense */ in pt_event_valid()
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| /linux-6.14.4/arch/arm/mm/ |
| D | proc-v7.S | 85 ALT_SMP(W(nop)) @ MP extensions imply L1 PTW
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| /linux-6.14.4/arch/mips/mm/ |
| D | tlbex.c | 2377 …pr_debug("PWSize (0x%0*lx): PS: 0x%lx GDW: 0x%02lx UDW: 0x%02lx MDW: 0x%02lx PTW: 0x%02lx PT… in print_htw_config()
2405 * setup GDW and PTW appropriately. UDW and MDW will remain 0. in config_htw_params()
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| /linux-6.14.4/tools/perf/Documentation/ |
| D | perf-intel-pt.txt | 501 *ptw*::
1013 recorded only if the "ptw" config term was used. Refer to the <<_config_terms,config terms>>
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| /linux-6.14.4/arch/arm64/kernel/ |
| D | cpufeature.c | 1850 * PTW barfs on the nVHE EL2 S1 page table format. Pretend in has_nv1()
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