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/linux-6.14.4/Documentation/gpu/amdgpu/display/
Ddisplay-manager.rst8 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
11 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
17 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
20 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
26 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
29 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
32 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
38 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
41 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
47 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
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Dprogramming-model-dcn.rst22 problem is well-defined, it will probably be implemented at the hardware level.
24 a very well-defined scope, the solution is usually implemented as a policy at
44 Unfortunately, there is no straight-forward analytic way to determine if a
65 .. kernel-figure:: dc-components.svg
67 The first layer of the diagram is the high-level DC API represented by the
72 API (`dc/inc/hw`), which represents each DCN low-level block, such as HUBP,
78 -------------
84 .. kernel-figure:: dc-arch-overview.svg
92 is a low-level abstraction for the connector. One interesting aspect of the
94 platform/board and not by the SoC. The `dc_link` struct is the high-level data
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Ddcn-overview.rst12 .. kernel-figure:: dc_pipeline_overview.svg
21 * **Display Pipe and Plane (DPP)**: This block provides pre-blend pixel
25 * **Multiple Pipe/Plane Combined (MPC)**: This component performs blending of
26 multiple planes, using global or per-pixel alpha.
40 * **Multi-Media HUB (MMHUBBUB)**: Memory controller interface for DMCUB and DWB
45 the Display Micro-Controller Unit - version B (DMCUB), which is handled via
86 ----------------------
102 a one-to-one mapping of the link encoder to PHY, but we can configure the DCN
108 ---------
116 representation and convert them to a DCN specific floating-point format (i.e.,
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/linux-6.14.4/drivers/gpu/drm/amd/amdgpu/
Damdgpu_mode.h40 #include <linux/i2c-algo-bit.h>
128 /* amdgpu gpio-based i2c
150 /* uses multi-media i2c engine */
317 /* DVI-I properties */
346 /* Driver-private color mgmt props */
350 * blending.
354 * size of degamma LUT as supported by the driver (read-only).
358 * @plane_degamma_tf_property: Plane pre-defined transfer function to
369 * @shaper_lut_property: Plane property to set pre-blending shaper LUT
372 * combine the user LUT values with pre-defined TF into the LUT
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/linux-6.14.4/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_color.c38 * - Input gamma LUT (de-normalized)
39 * - Input CSC (normalized)
40 * - Surface degamma LUT (normalized)
41 * - Surface CSC (normalized)
42 * - Surface regamma LUT (normalized)
43 * - Output CSC (normalized)
49 * Plane CTM -> Plane degamma -> Plane CTM -> Plane regamma -> Plane CTM
58 * The pipe blending also happens after these blocks so we don't actually
59 * support any CRTC props with correct blending with multiple planes - but we
70 * Plane DGM Bypass -> Plane CTM Bypass -> Plane RGM Bypass -> ...
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Damdgpu_dm.h2 * Copyright (C) 2015-2020 Advanced Micro Devices, Inc. All rights reserved.
98 * struct dm_compressor_info - Buffer info used by frame buffer compression
112 * struct dmub_hpd_work - Handle time consuming work in low priority outbox IRQ
125 * struct vblank_control_work - Work data for vblank control
141 * struct idle_workqueue - Work data for periodic action in idle
155 * struct amdgpu_dm_backlight_caps - Information about backlight
175 * @min_input_signal: minimum possible input in range 0-255.
179 * @max_input_signal: maximum possible input in range 0-255.
201 * struct dal_allocation - Tracks mapped FB memory for SMU communication
215 * struct hpd_rx_irq_offload_work_queue - Work queue to handle hpd_rx_irq
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Damdgpu_dm_plane.c1 // SPDX-License-Identifier: MIT
97 return amdgpu_lookup_format_info(cmd->pixel_format, cmd->modifier[0]); in amdgpu_dm_plane_get_format_info()
110 if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI || in amdgpu_dm_plane_fill_blending_from_plane_state()
111 plane_state->pixel_blend_mode == DRM_MODE_BLEND_COVERAGE) { in amdgpu_dm_plane_fill_blending_from_plane_state()
122 uint32_t format = plane_state->fb->format->format; in amdgpu_dm_plane_fill_blending_from_plane_state()
132 if (*per_pixel_alpha && plane_state->pixel_blend_mode == DRM_MODE_BLEND_COVERAGE) in amdgpu_dm_plane_fill_blending_from_plane_state()
136 if (plane_state->alpha < 0xffff) { in amdgpu_dm_plane_fill_blending_from_plane_state()
138 *global_alpha_value = plane_state->alpha >> 8; in amdgpu_dm_plane_fill_blending_from_plane_state()
147 if (*cap - *size < 1) { in amdgpu_dm_plane_add_modifier()
193 tiling_info->gfxversion = DcGfxVersion8; in amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags()
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/linux-6.14.4/drivers/gpu/drm/
Ddrm_blend.c6 * DRM core plane blending related functions
43 * sub-pixel accuracy, which is scaled up to a pixel-aligned destination
96 * plane-wide opacity, from transparent (0) to opaque (0xffff). It can be
99 * pre-multiplied by the global alpha associated to the plane.
109 * "rotate-<degrees>":
113 * "reflect-<axis>":
117 * reflect-x::
120 * | | -> | |
123 * reflect-y::
126 * | | -> | |
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Ddrm_connector.c52 * Hence they are reference-counted using drm_connector_get() and
68 * For connectors which are not fixed (like built-in panels) the driver needs to
77 * Note drm_connector_[un]register() first take connector->lock and then
95 { DRM_MODE_CONNECTOR_DVII, "DVI-I" },
96 { DRM_MODE_CONNECTOR_DVID, "DVI-D" },
97 { DRM_MODE_CONNECTOR_DVIA, "DVI-A" },
104 { DRM_MODE_CONNECTOR_HDMIA, "HDMI-A" },
105 { DRM_MODE_CONNECTOR_HDMIB, "HDMI-B" },
133 * drm_get_connector_type_name - return a string for connector type
148 * drm_connector_get_cmdline_mode - reads the user's cmdline mode
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/linux-6.14.4/Documentation/devicetree/bindings/display/
Damlogic,meson-vpu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <[email protected]>
17 DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
19 D |-------| |----| | | | | HDMI PLL |
20 D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
21 R |-------| |----| Processing | | | | |
22 | osd2 | | | |---| Enci ----------|----|-----VDAC------|
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/linux-6.14.4/drivers/gpu/drm/amd/display/dc/inc/hw/
Dmpc.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
30 * that performs blending of multiple planes, using global and per-pixel alpha.
31 * It also performs post-blending color correction operations according to the
36 * supporting "M MPC inputs -> N MPC outputs" flexible composition
39 * - Programmable blending structure to allow software controlled blending and
41 * - Programmable window location of each DPP in active region of display;
42 * - Combining multiple DPP pipes in one active region when a single DPP pipe
44 * - Combining multiple DPP from different SLS with blending;
45 * - Stereo formats from single DPP in top-bottom or side-by-side modes;
46 * - Stereo formats from 2 DPPs;
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/linux-6.14.4/drivers/staging/media/ipu3/include/uapi/
Dintel-ipu3.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2 /* Copyright (C) 2017 - 2018 Intel Corporation */
11 /* Vendor specific - used for IPU3 camera sub-system */
17 /* from include/uapi/linux/v4l2-controls.h */
26 #define IPU3_UAPI_GRID_START_MASK ((1 << 12) - 1)
34 * struct ipu3_uapi_grid_config - Grid plane config
56 * create a grid-based output, and the data is then divided into "slices".
71 * struct ipu3_uapi_awb_set_item - Memory layout for each cell in AWB
108 * struct ipu3_uapi_awb_raw_buffer - AWB raw buffer
119 * struct ipu3_uapi_awb_config_s - AWB config
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/linux-6.14.4/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
Ddcn201_hwseq.c44 hws->ctx
47 hws->regs->reg
50 dc->ctx->logger
54 hws->shifts->field_name, hws->masks->field_name
59 struct dc_plane_state *plane_state = pipe_ctx->plane_state; in patch_address_for_sbs_tb_stereo()
60 bool sec_split = pipe_ctx->top_pipe && in patch_address_for_sbs_tb_stereo()
61 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; in patch_address_for_sbs_tb_stereo()
63 if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO && in patch_address_for_sbs_tb_stereo()
64 (pipe_ctx->stream->timing.timing_3d_format == in patch_address_for_sbs_tb_stereo()
66 pipe_ctx->stream->timing.timing_3d_format == in patch_address_for_sbs_tb_stereo()
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/linux-6.14.4/drivers/gpu/drm/vkms/
Dvkms_composer.c1 // SPDX-License-Identifier: GPL-2.0+
20 new_color = (src * 0xffff + dst * (0xffff - alpha)); in pre_mul_blend_channel()
26 * pre_mul_alpha_blend - alpha blending equation
36 * pre-multiplied with the alpha channel values. See more
43 struct pixel_argb_u16 *out = &output_buffer->pixels[x_start]; in pre_mul_alpha_blend()
44 const struct pixel_argb_u16 *in = &stage_buffer->pixels[x_start]; in pre_mul_alpha_blend()
58 for (size_t i = 0; i < output_buffer->n_pixels; i++) in fill_background()
59 output_buffer->pixels[i] = *background_color; in fill_background()
62 // lerp(a, b, t) = a + (b - a) * t
68 s64 delta = drm_fixp_mul(b_fp - a_fp, t); in lerp_u16()
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/linux-6.14.4/drivers/gpu/drm/amd/display/dc/inc/
Dresource.h38 #define IS_PIPE_SYNCD_VALID(pipe) ((((pipe)->pipe_idx_syncd) & 0x80)?1:0)
39 #define GET_PIPE_SYNCD_FROM_PIPE(pipe) ((pipe)->pipe_idx_syncd & 0x7F)
40 #define SET_PIPE_SYNCD_TO_PIPE(pipe, pipe_syncd) ((pipe)->pipe_idx_syncd = (0x80 | pipe_syncd))
155 #define FREE_PIPE_INDEX_NOT_FOUND -1
203 * Inter-pipe Relation
207 * | 0 | -------------MPC---------ODM----------- |
209 * | 1 | ------------- | | | |
211 * | 2 | -------------MPC--------- | |
213 * | 3 | ------------- | | |
215 * | 4 | | ----------------------- |
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/linux-6.14.4/Documentation/admin-guide/media/
Dimx.rst1 .. SPDX-License-Identifier: GPL-2.0
7 ------------
15 - Image DMA Controller (IDMAC)
16 - Camera Serial Interface (CSI)
17 - Image Converter (IC)
18 - Sensor Multi-FIFO Controller (SMFC)
19 - Image Rotator (IRT)
20 - Video De-Interlacing or Combining Block (VDIC)
26 re-ordering (for example UYVY to YUYV) within the same colorspace, and
27 packed <--> planar conversion. The IDMAC can also perform a simple
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/linux-6.14.4/drivers/gpu/drm/renesas/rcar-du/
Drcar_du_group.c1 // SPDX-License-Identifier: GPL-2.0+
3 * R-Car Display Unit Channels Pair
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
11 * The R8A7779 DU is split in per-CRTC resources (scan-out engine, blending
12 * unit, timings generator, ...) and device-global resources (start/stop
19 * modeled as a single device with three CRTCs, two sets of "semi-global"
20 * resources, and a few device-global resources.
23 * counterpart in the DU documentation, that models those semi-global resources.
35 return rcar_du_read(rgrp->dev, rgrp->mmio_offset + reg); in rcar_du_group_read()
40 rcar_du_write(rgrp->dev, rgrp->mmio_offset + reg, data); in rcar_du_group_write()
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/linux-6.14.4/drivers/gpu/drm/sprd/
Dsprd_dpu.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/dma-buf.h>
130 struct dpu_context *ctx = &dpu->ctx; in dpu_wait_stop_done()
133 if (ctx->stopped) in dpu_wait_stop_done()
136 rc = wait_event_interruptible_timeout(ctx->wait_queue, ctx->evt_stop, in dpu_wait_stop_done()
138 ctx->evt_stop = false; in dpu_wait_stop_done()
140 ctx->stopped = true; in dpu_wait_stop_done()
143 drm_err(dpu->drm, "dpu wait for stop done time out!\n"); in dpu_wait_stop_done()
144 return -ETIMEDOUT; in dpu_wait_stop_done()
152 struct dpu_context *ctx = &dpu->ctx; in dpu_wait_update_done()
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/linux-6.14.4/drivers/gpu/drm/rockchip/
Drockchip_drm_vop.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author:Mark Yao <mark.yao@rock-chips.com>
45 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name)
47 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name)
49 vop_reg_set(vop, &win->phy->scl->ext->name, \
50 win->base, ~0, v, #name)
54 if (win_yuv2yuv && win_yuv2yuv->name.mask) \
55 vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \
60 if (win_yuv2yuv && win_yuv2yuv->phy->name.mask) \
61 vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \
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/linux-6.14.4/drivers/gpu/drm/nouveau/
Dnouveau_bo.c30 #include <linux/dma-mapping.h>
52 * NV10-NV40 tiling helpers
60 int i = reg - drm->tile.reg; in nv10_bo_update_tile_region()
62 struct nvkm_fb_tile *tile = &fb->tile.region[i]; in nv10_bo_update_tile_region()
64 nouveau_fence_unref(&reg->fence); in nv10_bo_update_tile_region()
66 if (tile->pitch) in nv10_bo_update_tile_region()
79 struct nouveau_drm_tile *tile = &drm->tile.reg[i]; in nv10_bo_get_tile_region()
81 spin_lock(&drm->tile.lock); in nv10_bo_get_tile_region()
83 if (!tile->used && in nv10_bo_get_tile_region()
84 (!tile->fence || nouveau_fence_done(tile->fence))) in nv10_bo_get_tile_region()
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/linux-6.14.4/Documentation/driver-api/media/drivers/
Dcx2341x-devel.rst1 .. SPDX-License-Identifier: GPL-2.0
7 -----------------------
12 .. note:: the memory long words are little-endian ('intel format').
21 .. code-block:: none
23 ivtvctl -O min=0x02000000,max=0x020000ff
26 register space :-).
35 .. code-block:: none
37 0x00000000-0x00ffffff Encoder memory space
38 0x00000000-0x0003ffff Encode.rom
39 ???-??? MPEG buffer(s)
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/linux-6.14.4/drivers/gpu/drm/amd/display/dc/core/
Ddc_resource.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
95 dc->ctx->logger
100 #define UNABLE_TO_SPLIT -1
230 init_data->num_virtual_links, dc); in dc_create_resource_pool()
234 init_data->num_virtual_links, dc); in dc_create_resource_pool()
238 init_data->num_virtual_links, dc); in dc_create_resource_pool()
243 init_data->num_virtual_links, dc); in dc_create_resource_pool()
247 init_data->num_virtual_links, dc); in dc_create_resource_pool()
251 init_data->num_virtual_links, dc); in dc_create_resource_pool()
255 init_data->num_virtual_links, dc); in dc_create_resource_pool()
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/linux-6.14.4/drivers/gpu/drm/amd/include/
Datomfirmware.h6 * Description header file of general definitions for OS and pre-OS video drivers
31 * If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the chan…
32 * If a change is needed for both pre and post SoC15 products, then the change has to be made separa…
115 ATOM_SCALER_DISABLE =0, /*scaler bypass mode, auto-center & no replication*/
116 ATOM_SCALER_CENTER =1, //For Fudo, it's bypass and auto-center & auto replication
117 ATOM_SCALER_EXPANSION =2, /*scaler expansion by 2 tap alpha blending mode*/
202 #define BIOS_VERSION_PREFIX "ATOMBIOSBK-AMD"
245 …tom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios,
604 uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt
605 uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt
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Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
109 #define ATOM_SCALER_EXPANSION 2 //For Fudo, it's 2 Tap alpha blending mode
110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,…
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
427 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
433 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
440 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
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/linux-6.14.4/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
Ddcn401_hwseq.c1 // SPDX-License-Identifier: MIT
41 hws->ctx
43 hws->regs->reg
45 dc->ctx->logger
50 hws->shifts->field_name, hws->masks->field_name
54 struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk; in dcn401_initialize_min_clocks()
56 clocks->dcfclk_deep_sleep_khz = DCN3_2_DCFCLK_DS_INIT_KHZ; in dcn401_initialize_min_clocks()
57 clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000; in dcn401_initialize_min_clocks()
58 clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000; in dcn401_initialize_min_clocks()
59 clocks->dramclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].memclk_mhz * 1000; in dcn401_initialize_min_clocks()
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