Searched +full:pr +full:- +full:decoupler (Results 1 – 4 of 4) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/fpga/xlnx,pr-decoupler.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Xilinx LogiCORE Partial Reconfig Decoupler/AXI shutdown manager Softcore10 - Nava kishore Manne <[email protected]>13 - $ref: fpga-bridge.yaml#16 The Xilinx LogiCORE Partial Reconfig(PR) Decoupler manages one or more22 is compatible with the Xilinx LogiCORE pr-decoupler. The Dynamic Function24 bridge. The controller safely handles AXI4MM and AXI4-Lite interfaces on a[all …]
1 // SPDX-License-Identifier: GPL-2.0-only7 * Decoupler IP Core.17 #include <linux/fpga/fpga-bridge.h>36 writel(val, d->io_base + offset); in xlnx_pr_decoupler_write()42 return readl(d->io_base + offset); in xlnx_pr_decouple_read()48 struct xlnx_pr_decoupler_data *priv = bridge->priv; in xlnx_pr_decoupler_enable_set()50 err = clk_enable(priv->clk); in xlnx_pr_decoupler_enable_set()59 clk_disable(priv->clk); in xlnx_pr_decoupler_enable_set()66 const struct xlnx_pr_decoupler_data *priv = bridge->priv; in xlnx_pr_decoupler_enable_show()70 err = clk_enable(priv->clk); in xlnx_pr_decoupler_enable_show()[all …]
1 # SPDX-License-Identifier: GPL-2.0-only52 FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V,100 tristate "Technologic Systems TS-73xx SBC FPGA Manager"104 present on the TS-73xx SBC boards.129 tristate "Xilinx LogiCORE PR Decoupler"133 Say Y to enable drivers for Xilinx LogiCORE PR Decoupler135 The PR Decoupler exists in the FPGA fabric to isolate one140 safely handles AXI4MM and AXI4-Lite interfaces on a173 Select this option to enable common support for Field-Programmable222 the card. It also instantiates the SPI master (spi-altera) for[all …]
1 # SPDX-License-Identifier: GPL-2.07 obj-$(CONFIG_FPGA) += fpga-mgr.o10 obj-$(CONFIG_FPGA_MGR_ALTERA_CVP) += altera-cvp.o11 obj-$(CONFIG_FPGA_MGR_ALTERA_PS_SPI) += altera-ps-spi.o12 obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o13 obj-$(CONFIG_FPGA_MGR_MACHXO2_SPI) += machxo2-spi.o14 obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o15 obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o16 obj-$(CONFIG_FPGA_MGR_STRATIX10_SOC) += stratix10-soc.o17 obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o[all …]