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/linux-6.14.4/Documentation/devicetree/bindings/soundwire/
Dqcom,soundwire.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <[email protected]>
11 - Srinivasa Rao Mandadapu <[email protected]>
19 - qcom,soundwire-v1.3.0
20 - qcom,soundwire-v1.5.0
21 - qcom,soundwire-v1.5.1
22 - qcom,soundwire-v1.6.0
23 - qcom,soundwire-v1.7.0
[all …]
/linux-6.14.4/drivers/net/ethernet/netronome/nfp/nfpcore/
Dnfp_nsp_eth.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /* Copyright (C) 2015-2017 Netronome Systems, Inc. */
84 __le64 control; member
128 dst[ETH_ALEN - i - 1] = src[i]; in nfp_eth_copy_mac_reverse()
139 port = le64_to_cpu(src->port); in nfp_eth_port_translate()
140 state = le64_to_cpu(src->state); in nfp_eth_port_translate()
142 dst->eth_index = FIELD_GET(NSP_ETH_PORT_INDEX, port); in nfp_eth_port_translate()
143 dst->index = index; in nfp_eth_port_translate()
144 dst->nbi = index / NSP_ETH_NBI_PORT_COUNT; in nfp_eth_port_translate()
145 dst->base = index % NSP_ETH_NBI_PORT_COUNT; in nfp_eth_port_translate()
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/phy/
Dnvidia,tegra124-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <[email protected]>
11 - Jon Hunter <[email protected]>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
17 documentation. Each such "pad" may control either one or multiple lanes,
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
[all …]
Dnvidia,tegra186-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <[email protected]>
11 - Jon Hunter <[email protected]>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
17 documentation. Each such "pad" may control either one or multiple lanes,
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
[all …]
Dnvidia,tegra194-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <[email protected]>
11 - Jon Hunter <[email protected]>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
17 documentation. Each such "pad" may control either one or multiple lanes,
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
[all …]
Dnvidia,tegra210-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <[email protected]>
11 - Jon Hunter <[email protected]>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
17 documentation. Each such "pad" may control either one or multiple lanes,
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/media/i2c/
Dmaxim,max96714.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Maxim MAX96714 GMSL2 to CSI-2 Deserializer
11 - Julien Massot <[email protected]>
15 CSI-2 D-PHY formatted output. The device allows the GMSL2 link to
16 simultaneously transmit bidirectional control-channel data while forward
18 remotely located serializer using industry-standard coax or STP
30 - const: maxim,max96714f
31 - items:
[all …]
Dmaxim,max96717.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MAX96717 CSI-2 to GMSL2 Serializer
11 - Julien Massot <[email protected]>
14 The MAX96717 serializer converts MIPI CSI-2 D-PHY formatted input
16 simultaneously transmit bidirectional control-channel data while forward
18 remotely located deserializer using industry-standard coax or STP
32 - const: maxim,max96717f
33 - items:
[all …]
/linux-6.14.4/drivers/thunderbolt/
Dacpi.c1 // SPDX-License-Identifier: GPL-2.0
26 fwnode = fwnode_find_reference(acpi_fwnode_handle(adev), "usb4-host-interface", 0); in tb_acpi_add_link()
31 if (dev_fwnode(&nhi->pdev->dev) != fwnode) in tb_acpi_add_link()
35 * Ignore USB3 ports here as USB core will set up device links between in tb_acpi_add_link()
37 * USB3 ports might not even have a physical device yet if xHCI driver in tb_acpi_add_link()
58 pm_runtime_get_sync(&pdev->dev); in tb_acpi_add_link()
60 link = device_link_add(&pdev->dev, &nhi->pdev->dev, in tb_acpi_add_link()
65 dev_dbg(&nhi->pdev->dev, "created link from %s\n", in tb_acpi_add_link()
66 dev_name(&pdev->dev)); in tb_acpi_add_link()
69 dev_warn(&nhi->pdev->dev, "device link creation from %s failed\n", in tb_acpi_add_link()
[all …]
Dswitch.c1 // SPDX-License-Identifier: GPL-2.0
3 * Thunderbolt driver - switch/port utility functions
12 #include <linux/nvmem-provider.h>
42 if (uuid_equal(&st->uuid, sw->uuid)) in __nvm_get_auth_status()
57 *status = st ? st->status : 0; in nvm_get_auth_status()
64 if (WARN_ON(!sw->uuid)) in nvm_set_auth_status()
75 memcpy(&st->uuid, sw->uuid, sizeof(st->uuid)); in nvm_set_auth_status()
76 INIT_LIST_HEAD(&st->list); in nvm_set_auth_status()
77 list_add_tail(&st->list, &nvm_auth_status_cache); in nvm_set_auth_status()
80 st->status = status; in nvm_set_auth_status()
[all …]
Dtb.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Thunderbolt driver - bus logic (NHI independent)
13 #include <linux/nvmem-provider.h>
31 * struct tb_nvm - Structure holding NVM information
38 * @non_active: Non-active portion NVMem device
79 * enum tb_switch_tmu_mode - TMU mode
81 * @TB_SWITCH_TMU_MODE_LOWRES: Uni-directional, normal mode
82 * @TB_SWITCH_TMU_MODE_HIFI_UNI: Uni-directional, HiFi mode
83 * @TB_SWITCH_TMU_MODE_HIFI_BI: Bi-directional, HiFi mode
84 * @TB_SWITCH_TMU_MODE_MEDRES_ENHANCED_UNI: Enhanced Uni-directional, MedRes mode
[all …]
/linux-6.14.4/drivers/soundwire/
Dgeneric_bandwidth_allocation.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 // Copyright(c) 2015-2020 Intel Corporation.
21 unsigned int lane; member
42 struct sdw_bus_params *b_params = &m_rt->bus->params; in sdw_compute_slave_ports()
44 port_bo = t_data->block_offset; in sdw_compute_slave_ports()
46 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { in sdw_compute_slave_ports()
47 rate = m_rt->stream->params.rate; in sdw_compute_slave_ports()
48 bps = m_rt->stream->params.bps; in sdw_compute_slave_ports()
49 sample_int = (m_rt->bus->params.curr_dr_freq / rate); in sdw_compute_slave_ports()
52 list_for_each_entry(p_rt, &s_rt->port_list, port_node) { in sdw_compute_slave_ports()
[all …]
/linux-6.14.4/drivers/phy/tegra/
Dxusb-tegra186.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
280 writel(value, priv->ao_regs + offset); in ao_writel()
285 return readl(priv->ao_regs + offset); in ao_readl()
304 return ERR_PTR(-ENOMEM); in tegra186_usb2_lane_probe()
306 INIT_LIST_HEAD(&usb2->base.list); in tegra186_usb2_lane_probe()
307 usb2->base.soc = &pad->soc->lanes[index]; in tegra186_usb2_lane_probe()
308 usb2->base.index = index; in tegra186_usb2_lane_probe()
309 usb2->base.pad = pad; in tegra186_usb2_lane_probe()
[all …]
/linux-6.14.4/include/linux/soundwire/
Dsdw.h1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
66 * constants for flow control, ports and transport
85 * enum sdw_slave_status - Slave status
103 * @SDW_CLK_PRE_DEPREPARE: pre clock stop de-prepare
104 * @SDW_CLK_POST_DEPREPARE: post clock stop de-prepare
114 * enum sdw_command_response - Command response as defined by SDW spec
200 * enum sdw_p15_behave - Slave Port 15 behaviour when the Master attempts a
211 * enum sdw_dpn_type - Data port types
226 * enum sdw_clk_stop_mode - Clock Stop modes
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/pci/
Dmvebu-pci.txt5 - compatible: one of the following values:
6 marvell,armada-370-pcie
7 marvell,armada-xp-pcie
8 marvell,dove-pcie
9 marvell,kirkwood-pcie
10 - #address-cells, set to <3>
11 - #size-cells, set to <2>
12 - #interrupt-cells, set to <1>
13 - bus-range: PCI bus numbers covered
14 - device_type, set to "pci"
[all …]
Dmediatek,mt7621-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/mediatek,mt7621-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sergio Paracuellos <[email protected]>
14 with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link
18 .-------.
22 '-------'
27 .------------------.
28 .-----------| HOST/PCI Bridge |------------.
[all …]
/linux-6.14.4/drivers/phy/marvell/
Dphy-mvebu-a3700-comphy.c1 // SPDX-License-Identifier: GPL-2.0
11 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
40 * When accessing common PHY lane registers directly, we need to shift by 1,
41 * since the registers are 16-bit.
175 * This register is not from PHY lane register space. It only exists in the
176 * indirect register space, before the actual PHY lane 2 registers. So the
184 #define COMPHY_PHY_REG(lane, reg) (((1 - (lane)) * 0x28) + ((reg) & 0x3f)) argument
227 unsigned int lane; member
234 .lane = _lane, \
246 /* lane 0 */
[all …]
/linux-6.14.4/Documentation/driver-api/media/drivers/
Dipu6.rst1 .. SPDX-License-Identifier: GPL-2.0
27 driver to control the IPU6, it also allows IPU6 access the system memory to
34 ------------------------
37 Buttress frequency control register for ISYS and PSYS
51 ---------
61 -------------------------------------
76 -----------------
80 Buttress with a copy of the SoC time, this counter maintains the up-to-date time
90 32-bit virtual address space. The IPU6 has MMU address translation hardware to
94 IPU6 driver. The IPU6 driver sets the level-1 page table base address to MMU
[all …]
/linux-6.14.4/drivers/usb/host/
Dxhci-hub.c1 // SPDX-License-Identifier: GPL-2.0
18 #include "xhci-trace.h"
24 /* Default sublink speed attribute of each lane */
54 bos->bLength = USB_DT_BOS_SIZE; in xhci_create_usb3x_bos_desc()
55 bos->bDescriptorType = USB_DT_BOS; in xhci_create_usb3x_bos_desc()
56 bos->wTotalLength = cpu_to_le16(USB_DT_BOS_SIZE + in xhci_create_usb3x_bos_desc()
58 bos->bNumDeviceCaps = 1; in xhci_create_usb3x_bos_desc()
61 for (i = 0; i < xhci->num_port_caps; i++) { in xhci_create_usb3x_bos_desc()
62 u8 major = xhci->port_caps[i].maj_rev; in xhci_create_usb3x_bos_desc()
63 u8 minor = xhci->port_caps[i].min_rev; in xhci_create_usb3x_bos_desc()
[all …]
/linux-6.14.4/Documentation/driver-api/soundwire/
Dsummary.rst10 SoundWire is a 2-pin multi-drop interface with data and clock line. It
14 (1) Transporting all of payload data channels, control information, and setup
15 commands over a single two-pin interface.
23 (4) Device status monitoring, including interrupt-style alerts to the Master.
27 Slaves can support up to 14 Data Ports. 13 Data Ports are dedicated to audio
28 transport. Data Port0 is dedicated to transport of Bulk control information,
29 each of the audio Data Ports (1..14) can support up to 8 Channels in
38 +---------------+ +---------------+
40 | Master |-------+-------------------------------| Slave |
42 | |-------|-------+-----------------------| |
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/net/
Dfsl,fman-dtsec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,fman-dtsec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Madalin Bucur <[email protected]>
15 10/100/1000 MBit/s speeds, and the 10-Gigabit Ethernet Media Access Controller
22 - fsl,fman-dtsec
23 - fsl,fman-xgec
24 - fsl,fman-memac
26 cell-index:
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/connector/
Dusb-connector.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/connector/usb-connector.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <[email protected]>
20 - enum:
21 - usb-a-connector
22 - usb-b-connector
23 - usb-c-connector
25 - items:
[all …]
/linux-6.14.4/Documentation/ABI/stable/
Dsysfs-class-infiniband2 -------------------------------------------------
9 Contact: linux-[email protected]
24 Contact: linux-[email protected]
34 Contact: linux-[email protected]
39 What: /sys/class/infiniband/<device>/ports/<port-num>/lid
40 What: /sys/class/infiniband/<device>/ports/<port-num>/rate
41 What: /sys/class/infiniband/<device>/ports/<port-num>/lid_mask_count
42 What: /sys/class/infiniband/<device>/ports/<port-num>/sm_sl
43 What: /sys/class/infiniband/<device>/ports/<port-num>/sm_lid
44 What: /sys/class/infiniband/<device>/ports/<port-num>/state
[all …]
/linux-6.14.4/Documentation/ABI/testing/
Dsysfs-bus-usb10 This allows to avoid side-effects with drivers
28 drivers, non-authorized one are not. By default, wired
33 Contact: linux-[email protected]
67 What: /sys/bus/usb-serial/drivers/.../new_id
69 Contact: linux-[email protected]
72 extra bus folder "usb-serial" in sysfs; apart from that
97 If CONFIG_PM is set and a USB 2.0 lpm-capable device is plugged
113 If CONFIG_PM is set and a USB 3.0 lpm-capable device is plugged
141 attribute allows user-space to know whether the device is
145 an on-screen keyboard if the only wireless keyboard is
[all …]
/linux-6.14.4/drivers/media/i2c/adv748x/
Dadv748x.h1 /* SPDX-License-Identifier: GPL-2.0+ */
14 * Analog HDMI MHL 4-Lane 1-Lane
48 * The ADV748X ports define the mapping between subdevices
93 #define is_tx_enabled(_tx) ((_tx)->state->endpoints[(_tx)->port] != NULL)
94 #define is_txa(_tx) ((_tx) == &(_tx)->state->txa)
95 #define is_txb(_tx) ((_tx) == &(_tx)->state->txb)
99 ((_state)->endpoints[ADV748X_PORT_AIN0] != NULL || \
100 (_state)->endpoints[ADV748X_PORT_AIN1] != NULL || \
101 (_state)->endpoints[ADV748X_PORT_AIN2] != NULL || \
102 (_state)->endpoints[ADV748X_PORT_AIN3] != NULL || \
[all …]

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