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/linux-6.14.4/rust/kernel/net/
Dphy.rs1 // SPDX-License-Identifier: GPL-2.0
5 //! Network PHY device.
7 //! C headers: [`include/linux/phy.h`](srctree/include/linux/phy.h).
14 /// PHY state machine states.
18 /// Some of PHY drivers access to the state of PHY's software state machine.
20 /// [`enum phy_state`]: srctree/include/linux/phy.h
23 /// PHY device and driver are not ready for anything.
25 /// PHY is ready to send and receive packets.
27 /// PHY is up, but no polling or interrupts are done.
29 /// PHY is up, but is in an error state.
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/linux-6.14.4/Documentation/devicetree/bindings/mmc/
Dmarvell,xenon-sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/marvell,xenon-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 mmc-controller.yaml and the properties used by the Xenon implementation.
15 sets, clock and PHY.
20 - Ulf Hansson <[email protected]>
25 - enum:
26 - marvell,armada-cp110-sdhci
27 - marvell,armada-ap806-sdhci
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/linux-6.14.4/Documentation/devicetree/bindings/phy/
Dphy-lpc18xx-usb-otg.txt1 NXP LPC18xx/43xx internal USB OTG PHY binding
2 ---------------------------------------------
4 This file contains documentation for the internal USB OTG PHY found
8 - compatible : must be "nxp,lpc1850-usb-otg-phy"
9 - clocks : must be exactly one entry
10 See: Documentation/devicetree/bindings/clock/clock-bindings.txt
11 - #phy-cells : must be 0 for this phy
12 See: Documentation/devicetree/bindings/phy/phy-bindings.txt
14 The phy node must be a child of the creg syscon node.
18 compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";
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Dallwinner,sun9i-a80-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun9i-a80-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A80 USB PHY
10 - Chen-Yu Tsai <[email protected]>
11 - Maxime Ripard <[email protected]>
14 "#phy-cells":
18 const: allwinner,sun9i-a80-usb-phy
25 - maxItems: 1
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Drockchip,inno-usb2phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,inno-usb2phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip USB2.0 phy with inno IP block
10 - Heiko Stuebner <[email protected]>
15 - rockchip,px30-usb2phy
16 - rockchip,rk3128-usb2phy
17 - rockchip,rk3228-usb2phy
18 - rockchip,rk3308-usb2phy
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Dphy-cadence-torrent.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence Torrent SD0801 PHY
10 This binding describes the Cadence SD0801 PHY (also known as Torrent PHY)
12 PHY also supports multilink multiprotocol combinations including protocols
16 - Swapnil Jakhade <[email protected]>
17 - Yuti Amonkar <[email protected]>
22 - cdns,torrent-phy
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Dfsl,imx8-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8 SoC series PCIe PHY
10 - Richard Zhu <[email protected]>
13 "#phy-cells":
18 - fsl,imx8mm-pcie-phy
19 - fsl,imx8mp-pcie-phy
27 clock-names:
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Dmediatek,mt8365-csi-rx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,mt8365-csi-rx.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Mediatek Sensor Interface MIPI CSI CD-PHY
11 - Julien Stephan <[email protected]>
12 - Andy Hsieh <[email protected]>
15 The SENINF CD-PHY is a set of CD-PHY connected to the SENINF CSI-2
17 Depending on the SoC model, each PHYs can be either CD-PHY or D-PHY only
23 - mediatek,mt8365-csi-rx
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Dpistachio-usb-phy.txt1 IMG Pistachio USB PHY
5 --------------------
6 - compatible: Must be "img,pistachio-usb-phy".
7 - #phy-cells: Must be 0. See ./phy-bindings.txt for details.
8 - clocks: Must contain an entry for each entry in clock-names.
9 See ../clock/clock-bindings.txt for details.
10 - clock-names: Must include "usb_phy".
11 - img,cr-top: Must contain a phandle to the CR_TOP syscon node.
12 - img,refclk: Indicates the reference clock source for the USB PHY.
13 See <dt-bindings/phy/phy-pistachio-usb.h> for a list of valid values.
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Dphy-hisi-inno-usb2.txt1 Device tree bindings for HiSilicon INNO USB2 PHY
4 - compatible: Should be one of the following strings:
5 "hisilicon,inno-usb2-phy",
6 "hisilicon,hi3798cv200-usb2-phy".
7 - reg: Should be the address space for PHY configuration register in peripheral
9 - clocks: The phandle and clock specifier pair for INNO USB2 PHY device
11 - resets: The phandle and reset specifier pair for INNO USB2 PHY device reset
13 - #address-cells: Must be 1.
14 - #size-cells: Must be 0.
16 The INNO USB2 PHY device should be a child node of peripheral controller that
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Dqcom,snps-eusb2-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,snps-eusb2-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SNPS eUSB2 phy controller
10 - Abel Vesa <[email protected]>
18 - items:
19 - enum:
20 - qcom,sar2130p-snps-eusb2-phy
21 - qcom,sdx75-snps-eusb2-phy
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Drenesas,usb3-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,usb3-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car generation 3 USB 3.0 PHY
10 - Yoshihiro Shimoda <[email protected]>
15 - enum:
16 - renesas,r8a774a1-usb3-phy # RZ/G2M
17 - renesas,r8a774b1-usb3-phy # RZ/G2N
18 - renesas,r8a774e1-usb3-phy # RZ/G2H
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Dqcom,qusb2-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Qualcomm QUSB2 phy controller
11 - Wesley Cheng <[email protected]>
19 - items:
20 - enum:
21 - qcom,ipq5424-qusb2-phy
22 - qcom,ipq6018-qusb2-phy
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Dallwinner,suniv-f1c100s-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,suniv-f1c100s-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner F1C100s USB PHY
10 - Chen-Yu Tsai <[email protected]>
11 - Maxime Ripard <[email protected]>
14 "#phy-cells":
18 const: allwinner,suniv-f1c100s-usb-phy
22 description: PHY Control registers
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Dallwinner,sun8i-v3s-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-v3s-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner V3s USB PHY
10 - Chen-Yu Tsai <[email protected]>
11 - Maxime Ripard <[email protected]>
14 "#phy-cells":
18 const: allwinner,sun8i-v3s-usb-phy
22 - description: PHY Control registers
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/linux-6.14.4/Documentation/devicetree/bindings/usb/
Ddwc3-xilinx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mubin Sayyed <[email protected]>
11 - Radhey Shyam Pandey <[email protected]>
16 - enum:
17 - xlnx,zynqmp-dwc3
18 - xlnx,versal-dwc3
22 "#address-cells":
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Dti,keystone-dwc3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/ti,keystone-dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Roger Quadros <[email protected]>
15 - enum:
16 - ti,keystone-dwc3
17 - ti,am654-dwc3
22 '#address-cells':
25 '#size-cells':
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/linux-6.14.4/Documentation/devicetree/bindings/media/
Dnxp,imx-mipi-csi2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver
10 - Rui Miguel Silva <[email protected]>
11 - Laurent Pinchart <[email protected]>
13 description: |-
14 The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
19 While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is
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/linux-6.14.4/Documentation/devicetree/bindings/net/dsa/
Dmediatek,mt7530.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <[email protected]>
11 - Landen Chao <[email protected]>
12 - DENG Qingfang <[email protected]>
13 - Sean Wang <[email protected]>
14 - Daniel Golle <[email protected]>
17 There are three versions of MT7530, standalone, in a multi-chip module and
18 built-into a SoC.
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/linux-6.14.4/Documentation/devicetree/bindings/ata/
Dmediatek,mtk-ahci.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/ata/mediatek,mtk-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ryder Lee <[email protected]>
13 - $ref: ahci-common.yaml#
18 - enum:
19 - mediatek,mt7622-ahci
20 - const: mediatek,mtk-ahci
28 interrupt-names:
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/linux-6.14.4/Documentation/devicetree/bindings/clock/
Dqcom,dispcc-sm8x50.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jonathan Marek <[email protected]>
17 include/dt-bindings/clock/qcom,dispcc-sm8150.h
18 include/dt-bindings/clock/qcom,dispcc-sm8250.h
19 include/dt-bindings/clock/qcom,dispcc-sm8350.h
24 - qcom,sc8180x-dispcc
25 - qcom,sm8150-dispcc
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Dqcom,sa8775p-dispcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sa8775p-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Taniya Das <[email protected]>
16 See also: include/dt-bindings/clock/qcom,sa8775p-dispcc.h
21 - qcom,sa8775p-dispcc0
22 - qcom,sa8775p-dispcc1
26 - description: GCC AHB clock source
27 - description: Board XO source
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/linux-6.14.4/Documentation/devicetree/bindings/net/
Drenesas,ethertsn.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Ethernet TSN End-station
10 - Niklas Söderlund <[email protected]>
14 Gbps full-duplex link via MII/GMII/RMII/RGMII. Depending on the connected PHY.
17 - $ref: ethernet-controller.yaml#
22 - enum:
23 - renesas,r8a779g0-ethertsn # R-Car V4H
24 - const: renesas,rcar-gen4-ethertsn
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Dnvidia,tegra234-mgbe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra234 MGBE Multi-Gigabit Ethernet Controller
10 - Thierry Reding <[email protected]>
11 - Jon Hunter <[email protected]>
15 const: nvidia,tegra234-mgbe
20 reg-names:
22 - const: hypervisor
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/linux-6.14.4/arch/mips/boot/dts/mscc/
Docelot_pcb120.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/phy/phy-ocelot-serdes.h>
12 compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
15 stdout-path = "serial0:115200n8";
25 phy_int_pins: phy-int-pins {
30 phy_load_save_pins: phy-load-save-pins {
42 pinctrl-names = "default";
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