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/linux-6.14.4/include/linux/
Dpwm.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 * enum pwm_polarity - polarity of a PWM signal
17 * @PWM_POLARITY_NORMAL: a high signal for the duration of the duty-
19 * period
20 * @PWM_POLARITY_INVERSED: a low signal for the duration of the duty-
22 * period
30 * struct pwm_args - board-dependent PWM arguments
31 * @period: reference period
34 * This structure describes board-dependent arguments attached to a PWM
43 u64 period; member
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/linux-6.14.4/drivers/pwm/
Dpwm-sifive.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017-2018 SiFive
5 * Reference Manual : https://static.dev.sifive.com/FU540-C000-v1.0.pdf
8 * - When changing both duty cycle and period, we cannot prevent in
9 * software that the output might produce a period with mixed
10 * settings (new period length and old duty cycle).
11 * - The hardware cannot generate a 100% duty cycle.
12 * - The hardware generates only inverted output.
64 mutex_lock(&ddata->lock); in pwm_sifive_request()
65 ddata->user_count++; in pwm_sifive_request()
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Dpwm-stm32.c1 // SPDX-License-Identifier: GPL-2.0
7 * Inspired by timer-stm32.c from Maxime Coquelin
8 * pwm-atmel.c from Bo Shen
12 #include <linux/mfd/stm32-timers.h>
49 regmap_read(dev->regmap, TIM_CCER, &ccer); in active_channels()
68 unsigned int ch = pwm->hwpwm; in stm32_pwm_round_waveform_tohw()
73 if (wf->period_length_ns == 0) { in stm32_pwm_round_waveform_tohw()
81 ret = clk_enable(priv->clk); in stm32_pwm_round_waveform_tohw()
85 wfhw->ccer = TIM_CCER_CCxE(ch + 1); in stm32_pwm_round_waveform_tohw()
86 if (priv->have_complementary_output) in stm32_pwm_round_waveform_tohw()
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Dpwm-tegra.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/pwm/pwm-tegra.c
5 * Tegra pulse-width-modulation controller driver
7 * Copyright (c) 2010-2020, NVIDIA Corporation.
8 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <[email protected]>
11 * 1. 13-bit: Frequency division (SCALE)
12 * 2. 8-bit : Pulse division (DUTY)
13 * 3. 1-bit : Enable bit
21 * This 1.6 MHz frequency can further be divided using SCALE value in PWM.
28 * - When PWM is disabled, the output is driven to inactive.
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/linux-6.14.4/include/uapi/linux/netfilter/
Dxt_hashlimit.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
12 /* 1/10,000 sec period => max of 10,000/sec. Min rate is then 429490
16 /* packet length accounting is done in 16-byte steps */
34 __u32 avg; /* Average secs between packets * scale */
35 __u32 burst; /* Period multiplier for upper limit. */
58 __u32 avg; /* Average secs between packets * scale */
59 __u32 burst; /* Period multiplier for upper limit. */
71 __u64 avg; /* Average secs between packets * scale */
72 __u64 burst; /* Period multiplier for upper limit. */
85 __u64 avg; /* Average secs between packets * scale */
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Dxt_limit.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
12 /* 1/10,000 sec period => max of 10,000/sec. Min rate is then 429490
15 __u32 avg; /* Average secs between packets * scale */
16 __u32 burst; /* Period multiplier for upper limit. */
/linux-6.14.4/drivers/video/backlight/
Dpwm_bl.c1 // SPDX-License-Identifier: GPL-2.0-only
29 unsigned int scale; member
43 if (pb->enabled) in pwm_backlight_power_on()
46 if (pb->power_supply) { in pwm_backlight_power_on()
47 err = regulator_enable(pb->power_supply); in pwm_backlight_power_on()
49 dev_err(pb->dev, "failed to enable power supply\n"); in pwm_backlight_power_on()
52 if (pb->post_pwm_on_delay) in pwm_backlight_power_on()
53 msleep(pb->post_pwm_on_delay); in pwm_backlight_power_on()
55 gpiod_set_value_cansleep(pb->enable_gpio, 1); in pwm_backlight_power_on()
57 pb->enabled = true; in pwm_backlight_power_on()
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/linux-6.14.4/tools/testing/selftests/rcutorture/bin/
Dkvm-recheck-rcuscale.sh2 # SPDX-License-Identifier: GPL-2.0+
6 # Usage: kvm-recheck-rcuscale.sh resdir
13 if test -d "$i" -a -r "$i"
23 if kvm-recheck-rcuscale-ftrace.sh $i
29 configfile=`echo $i | sed -e 's/^.*\///'`
31 sed -e 's/^\[[^]]*]//' < $i/console.log |
33 /-scale: .* gps: .* batches:/ {
38 /-scale: .*writer-duration/ {
43 /rcu_scale: Grace-period kthread CPU time/ {
64 last = gptimes[1] - 10;
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/linux-6.14.4/drivers/iio/adc/
Dpac1921.c1 // SPDX-License-Identifier: GPL-2.0+
3 * IIO driver for PAC1921 High-Side Power/Current Monitor
63 /* Time from Sleep State to Start of Integration Period (tSLEEP_TO_INT) */
74 /* f7bb9932-86ee-4516-a236-7a7a742e55cb */
80 * Pre-computed scale factors for BUS voltage
84 * Vbus scale (mV) = max_vbus (mV) / dv_gain / resolution
96 * Pre-computed scales for SENSE voltage
100 * Vsense scale (mV) = max_vsense (mV) / di_gain / resolution
115 * integration period.
117 * Changing the number of samples affects the integration period: higher the
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Dti-ads1015.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * ADS1015 - Texas Instruments Analog-to-Digital Converter
7 * IIO driver for ADS1015 ADC 7-bit I2C slave address:
8 * * 0x48 - ADDR connected to Ground
9 * * 0x49 - ADDR connected to Vdd
10 * * 0x4A - ADDR connected to SDA
11 * * 0x4B - ADDR connected to SCL
85 const int *scale; member
111 * Translation from PGA bits to full-scale positive and negative input voltage
161 * Compile-time check whether _fitbits can accommodate up to _testbits
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/linux-6.14.4/drivers/thermal/
Dsun8i_thermal.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/nvmem-consumer.h>
55 #define SUN50I_THS_CTRL0_T_ACQ(x) (GENMASK(15, 0) & ((x) - 1))
56 #define SUN50I_THS_CTRL0_T_SAMPLE_PER(x) ((GENMASK(15, 0) & ((x) - 1)) << 16)
74 int scale; member
103 return tmdev->chip->offset - (reg * tmdev->chip->scale / 10); in sun8i_ths_calc_temp()
110 return -1191 * reg / 10 + 223000; in sun50i_h5_calc_temp()
112 return -1452 * reg / 10 + 259000; in sun50i_h5_calc_temp()
114 return -1590 * reg / 10 + 276000; in sun50i_h5_calc_temp()
120 struct ths_device *tmdev = s->tmdev; in sun8i_ths_get_temp()
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/linux-6.14.4/include/uapi/linux/netfilter_bridge/
Debt_limit.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
12 /* 1/10,000 sec period => max of 10,000/sec. Min rate is then 429490
16 __u32 avg; /* Average secs between packets * scale */
17 __u32 burst; /* Period multiplier for upper limit. */
/linux-6.14.4/Documentation/userspace-api/media/dvb/
Dfrontend-stat-properties.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _frontend-stat-properties:
32 - ``svalue`` or ``uvalue``, where ``svalue`` is for signed values of
34 (counters, relative scale)
36 - ``scale`` - Scale for the value. It can be:
38 - ``FE_SCALE_NOT_AVAILABLE`` - The parameter is supported by the
42 - ``FE_SCALE_DECIBEL`` - parameter is a signed value, measured in
45 - ``FE_SCALE_RELATIVE`` - parameter is a unsigned value, where 0
48 - ``FE_SCALE_COUNTER`` - parameter is a unsigned value that counts
53 .. _DTV-STAT-SIGNAL-STRENGTH:
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/linux-6.14.4/drivers/iio/light/
Dltr501.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Support for Lite-On LTR501 and similar ambient light and proximity sensors.
7 * 7-bit I2C slave address 0x23
35 #define LTR501_ALS_DATA1 0x88 /* 16-bit, little endian */
37 #define LTR501_ALS_DATA0 0x8a /* 16-bit, little endian */
40 #define LTR501_PS_DATA 0x8d /* 16-bit, little endian */
71 ((vis_coeff * vis_data) - (ir_coeff * ir_data))
95 #define LTR501_RESERVED_GAIN -1
105 int scale; member
159 int als_period, ps_period; /* period in micro seconds */
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Dapds9306.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * APDS-9306/APDS-9306-065 Ambient Light Sensor
5 * Datasheet: https://docs.broadcom.com/doc/AV02-4755EN
27 #include <linux/iio/iio-gts-helper.h>
57 #define APDS9306_ALS_THRES_VAL_MAX (BIT(20) - 1)
67 * struct part_id_gts_multiplier - Part no. and corresponding gts multiplier
69 * GTS (Gain Time Scale) are helper functions for Light sensors which along
90 * for apds9306 and 43 uW per sq cm (293.69 lux) for apds9306-065.
93 * Lux = (raw + offset) * scale; offset can be any value by userspace.
95 * Scale table by IIO GTS Helpers = (1 / HG) * (1 / ITG) * Multiplier.
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/linux-6.14.4/arch/loongarch/kvm/
Dtimer.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020-2023 Loongson Technology Corporation Limited
11 * ktime_to_tick() - Scale ktime_t to timer tick value.
18 return div_u64(delta * vcpu->arch.timer_mhz, MNSEC_PER_SEC); in ktime_to_tick()
23 return div_u64(tick * MNSEC_PER_SEC, vcpu->arch.timer_mhz); in tick_to_ns()
33 rcuwait_wake_up(&vcpu->wait); in kvm_swtimer_wakeup()
43 vcpu->arch.timer_mhz = timer_hz >> 20; in kvm_init_timer()
46 kvm_write_sw_gcsr(vcpu->arch.csr, LOONGARCH_CSR_TVAL, 0); in kvm_init_timer()
55 unsigned long ticks, delta, period; in kvm_restore_timer() local
57 struct loongarch_csrs *csr = vcpu->arch.csr; in kvm_restore_timer()
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/linux-6.14.4/include/linux/input/
Dadxl34x.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
22 * form with a scale factor of 15.6 mg/LSB (i.e. 0x7F = +2 g)
35 * tap_latency period, i.e. after the first tap but before the
49 * The data format is unsigned. The scale factor is 62.5 mg/LSB
60 * to qualify as a tap event. The scale factor is 625 us/LSB. A zero
70 * window tap_window for a possible second tap event. The scale
81 * tap can begin. The scale factor is 1.25 ms/LSB. A zero value will
126 * The data format is unsigned. The scale factor is
136 * detection. The data format is unsigned. The scale
147 * inactivity_threshold for inactivity to be declared. The scale factor
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/linux-6.14.4/drivers/gpu/drm/bridge/
Dti-sn65dsi86.c1 // SPDX-License-Identifier: GPL-2.0
134 * struct ti_sn65dsi86 - Platform data for ti-sn65dsi86 driver.
135 * @bridge_aux: AUX-bus sub device for MIPI-to-eDP bridge functionality.
136 * @gpio_aux: AUX-bus sub device for GPIO controller functionality.
137 * @aux_aux: AUX-bus sub device for eDP AUX channel functionality.
138 * @pwm_aux: AUX-bus sub device for PWM controller functionality.
153 * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG.
159 * serves double-duty of keeping track of the direction and
165 * each other's read-modify-write.
230 ret = regmap_bulk_read(pdata->regmap, reg, buf, ARRAY_SIZE(buf)); in ti_sn65dsi86_read_u16()
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/linux-6.14.4/drivers/ptp/
Dptp_dfl_tod.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * DFL device driver for Time-of-Day (ToD) private feature
77 * and TOD_ADJUST_COUNT register for in hardware. The dt->tod_lock spinlock must be
83 void __iomem *base = dt->tod_ctrl; in fine_adjust_tod_clock()
101 void __iomem *base = dt->tod_ctrl; in coarse_adjust_tod_clock()
130 void __iomem *base = dt->tod_ctrl; in dfl_tod_adjust_fine()
142 return -ERANGE; in dfl_tod_adjust_fine()
160 spin_lock_irqsave(&dt->tod_lock, flags); in dfl_tod_adjust_fine()
166 spin_unlock_irqrestore(&dt->tod_lock, flags); in dfl_tod_adjust_fine()
174 u32 period, diff, rem, rem_period, adj_period; in dfl_tod_adjust_time() local
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/linux-6.14.4/drivers/usb/dwc3/
Dcore.c1 // SPDX-License-Identifier: GPL-2.0
3 * core.c - DesignWare USB3 DRD Controller Core file
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
24 #include <linux/dma-mapping.h>
42 #include "../host/xhci-ext-caps.h"
47 * dwc3_get_dr_mode - Validates and sets dr_mode
53 struct device *dev = dwc->dev; in dwc3_get_dr_mode()
56 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) in dwc3_get_dr_mode()
57 dwc->dr_mode = USB_DR_MODE_OTG; in dwc3_get_dr_mode()
59 mode = dwc->dr_mode; in dwc3_get_dr_mode()
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/linux-6.14.4/drivers/gpu/drm/i915/display/
Dintel_backlight.c1 // SPDX-License-Identifier: MIT
28 * scale - scale values from one range to another
38 static u32 scale(u32 source_val, in scale() function
52 target_val = mul_u32_u32(source_val - source_min, in scale()
53 target_max - target_min); in scale()
54 target_val = DIV_ROUND_CLOSEST_ULL(target_val, source_max - source_min); in scale()
61 * Scale user_level in range [0..user_max] to [0..hw_max], clamping the result
67 struct intel_panel *panel = &connector->panel; in clamp_user_to_hw()
70 hw_level = scale(user_level, 0, user_max, 0, panel->backlight.max); in clamp_user_to_hw()
71 hw_level = clamp(hw_level, panel->backlight.min, panel->backlight.max); in clamp_user_to_hw()
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/linux-6.14.4/Documentation/devicetree/bindings/clock/
Dnvidia,tegra124-dfll.txt4 Documentation/devicetree/bindings/clock/clock-bindings.txt
7 the fast CPU cluster. It consists of a free-running voltage controlled
10 communicating with an off-chip PMIC either via an I2C bus or via PWM signals.
13 - compatible : should be one of:
14 - "nvidia,tegra124-dfll": for Tegra124
15 - "nvidia,tegra210-dfll": for Tegra210
16 - reg : Defines the following set of registers, in the order listed:
17 - registers for the DFLL control logic.
18 - registers for the I2C output logic.
19 - registers for the integrated I2C master controller.
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/linux-6.14.4/drivers/message/fusion/
Dmptspi.c6 * Copyright (c) 1999-2008 LSI Corporation
7 * (mailto:DL-[email protected])
10 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
24 LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
43 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
45 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
72 /*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
99 * mptspi_setTargetNegoParms - Update the target negotiation parameters
111 MPT_ADAPTER *ioc = hd->ioc; in mptspi_setTargetNegoParms()
112 SpiCfgData *pspi_data = &ioc->spi_data; in mptspi_setTargetNegoParms()
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/linux-6.14.4/drivers/leds/
Dleds-pca963x.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Author: Peter Meerwald <p.meerwald@bct-electronic.com>
9 * Based on leds-pca955x.c
11 * LED driver for the PCA9633 I2C LED driver (7-bit slave address 0x62)
12 * LED driver for the PCA9634/5 I2C LED driver (7-bit slave address set by hw.)
22 * or by adding the 'nxp,hw-blink' property to the DTS.
43 #define PCA963X_MODE2_OUTDRV 0x04 /* Open-drain or totem pole */
86 /* Total blink period in milliseconds */
121 struct i2c_client *client = led->chip->client; in pca963x_brightness()
122 struct pca963x_chipdef *chipdef = led->chip->chipdef; in pca963x_brightness()
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/linux-6.14.4/arch/arm/mach-omap2/
Dsdrc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
8 * Copyright (C) 2007-2008, 2012 Texas Instruments, Inc.
9 * Copyright (C) 2007-2008 Nokia Corporation
55 * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate
62 * This structure holds a pre-computed set of register values for the
64 * intended to be pre-computed and specified in an array in the board-*.c
112 /* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
124 /* SDRC register offsets - read/write with sdrc_{read,write}_reg() */
165 * As long as you scale down, most parameters are still work, they just
166 * become sub-optimal. The RFR value goes in the opposite direction. If you
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