Home
last modified time | relevance | path

Searched +full:pci +full:- +full:iommu (Results 1 – 25 of 367) sorted by relevance

12345678910>>...15

/linux-6.14.4/Documentation/devicetree/bindings/pci/
Dpci-iommu.txt2 relationship between PCI(e) devices and IOMMU(s).
4 Each PCI(e) device under a root complex is uniquely identified by its Requester
16 IOMMUs may distinguish PCI devices through sideband data derived from the
17 Requester ID. While a given PCI device can only master through one IOMMU, a
18 root complex may split masters across a set of IOMMUs (e.g. with one IOMMU per
22 and a mechanism is required to map from a PCI device to its IOMMU and sideband
25 For generic IOMMU bindings, see
26 Documentation/devicetree/bindings/iommu/iommu.txt.
29 PCI root complex
33 -------------------
[all …]
Dapple,pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/apple,pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Kettenis <[email protected]>
21 used to take the PCI devices on those ports out of reset. Therefore
22 the standard "reset-gpios" and "max-link-speed" properties appear on
23 the child nodes that represent the PCI bridges that correspond to
34 - enum:
35 - apple,t8103-pcie
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/virtio/
Dpci-iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/virtio/pci-iommu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: virtio-iommu device using the virtio-pci transport
10 - Jean-Philippe Brucker <jean-[email protected]>
13 When virtio-iommu uses the PCI transport, its programming interface is
14 discovered dynamically by the PCI probing infrastructure. However the
15 device tree statically describes the relation between IOMMU and DMA
16 masters. Therefore, the PCI root complex that hosts the virtio-iommu
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/iommu/
Driscv,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iommu/riscv,iommu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V IOMMU Architecture Implementation
10 - Tomasz Jeznach <[email protected]>
13 The RISC-V IOMMU provides memory address translation and isolation for
14 input and output devices, supporting per-device translation context,
17 It supports identical translation table format to the RISC-V address
19 Hardware uses in-memory command and fault reporting queues with wired
[all …]
Diommu.txt5 IOMMU device node:
8 An IOMMU can provide the following services:
13 Example: 32-bit DMA to 64-bit physical addresses
15 * Implement scatter-gather at page level granularity so that the device does
19 through the IOMMU and faulting when encountering accesses to unmapped
29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
30 typically have a fixed association to the master device, whereas multiple-
31 master IOMMU devices can translate accesses from more than one master.
33 The device tree node of the IOMMU device's parent bus must contain a valid
34 "dma-ranges" property that describes how the physical address space of the
[all …]
/linux-6.14.4/Documentation/driver-api/
Dvfio.rst2 VFIO - "Virtual Function I/O" [1]_
7 allotted. This includes x86 hardware with AMD-Vi and Intel VT-d,
9 systems such as Freescale PAMU. The VFIO driver is an IOMMU/device
11 a secure, IOMMU protected environment. In other words, this allows
12 safe [2]_, non-privileged, userspace drivers.
19 bare-metal device drivers [3]_.
22 field, also benefit from low-overhead, direct device access from
23 userspace. Examples include network adapters (often non-TCP/IP based)
27 which has no notion of IOMMU protection, limited interrupt support,
28 and requires root privileges to access things like PCI configuration
[all …]
/linux-6.14.4/drivers/acpi/
Dviot.c1 // SPDX-License-Identifier: GPL-2.0
6 * para-virtual IOMMUs and the endpoints they manage. The OS uses it to
8 * before their IOMMU is ready.
12 * VIOT driver looks for an IOMMU associated to the device in the VIOT table.
13 * If an IOMMU exists and has been initialized, the VIOT driver initializes the
14 * device's IOMMU fwspec, allowing the DMA infrastructure to invoke the IOMMU
15 * ops when the device driver configures DMA mappings. If an IOMMU exists and
16 * hasn't yet been initialized, VIOT returns -EPROBE_DEFER to postpone probing
17 * the device until the IOMMU is available.
23 #include <linux/iommu.h>
[all …]
/linux-6.14.4/drivers/iommu/riscv/
Diommu-pci.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright © 2022-2024 Rivos Inc.
5 * Copyright © 2023 FORTH-ICS/CARV
7 * RISCV IOMMU as a PCIe device
16 #include <linux/iommu.h>
18 #include <linux/pci.h>
20 #include "iommu-bits.h"
21 #include "iommu.h"
23 /* QEMU RISC-V IOMMU implementation */
26 /* Rivos Inc. assigned PCI Vendor and Device IDs */
[all …]
/linux-6.14.4/drivers/iommu/amd/
Damd_iommu_types.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
12 #include <linux/iommu.h>
19 #include <linux/pci.h>
21 #include <linux/io-pgtable.h>
52 /* Flag masks for the AMD IOMMU exclusion range */
116 * The current driver only support 16-bit PASID.
117 * Currently, hardware only implement upto 16-bit PASID
291 * to the IOMMU core, which will then use this information to split
300 /* Special mode where page-sizes are limited to 4 KiB */
[all …]
Dinit.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
8 #define pr_fmt(fmt) "AMD-Vi: " fmt
11 #include <linux/pci.h>
20 #include <linux/amd-iommu.h>
25 #include <asm/pci-direct.h>
26 #include <asm/iommu.h>
39 #include "../iommu-pages.h"
99 * structure describing one IOMMU in the ACPI table. Typically followed by one
119 * A device entry describing which devices a specific IOMMU translates and
[all …]
/linux-6.14.4/arch/sparc/kernel/
Dpsycho_common.c1 // SPDX-License-Identifier: GPL-2.0
2 /* psycho_common.c: Code common to PSYCHO and derivative PCI controllers.
39 struct strbuf *strbuf = &pbm->stc; in psycho_check_stc_error()
43 if (!strbuf->strbuf_control) in psycho_check_stc_error()
46 err_base = strbuf->strbuf_err_stat; in psycho_check_stc_error()
47 tag_base = strbuf->strbuf_tag_diag; in psycho_check_stc_error()
48 line_base = strbuf->strbuf_line_diag; in psycho_check_stc_error()
55 * before re-enabling the streaming buffer. If any dirty data in psycho_check_stc_error()
60 control = upa_readq(strbuf->strbuf_control); in psycho_check_stc_error()
61 upa_writeq(control | PSYCHO_STRBUF_CTRL_DENAB, strbuf->strbuf_control); in psycho_check_stc_error()
[all …]
Dpci_impl.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* pci_impl.h: Helper definitions for PCI controller support.
12 #include <linux/pci.h>
16 #include <asm/iommu.h>
18 /* The abstraction used here is that there are PCI controllers,
19 * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules
20 * underneath. Each PCI bus module uses an IOMMU (shared by both
21 * PBMs of a controller, or per-PBM), and if a streaming buffer
22 * is present, each PCI bus module has its own. (ie. the IOMMU
24 * Furthermore, each PCI bus module controls its own autonomous
[all …]
Dpci_schizo.c1 // SPDX-License-Identifier: GPL-2.0
2 /* pci_schizo.c: SCHIZO/TOMATILLO specific PCI controller support.
9 #include <linux/pci.h>
20 #include <asm/iommu.h>
49 /* IOMMU control register. */
56 #define SCHIZO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
57 #define SCHIZO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
58 #define SCHIZO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
59 #define SCHIZO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
60 #define SCHIZO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
[all …]
Dpci_psycho.c1 // SPDX-License-Identifier: GPL-2.0
2 /* pci_psycho.c: PSYCHO/U2P specific PCI controller support.
11 #include <linux/pci.h>
20 #include <asm/iommu.h>
33 /* Misc. PSYCHO PCI controller register offsets and definitions. */
49 #define PSYCHO_PCICTRL_SPEED 0x0000000200000000UL /* PCI speed (1 is U2P clock) */
51 #define PSYCHO_PCICTRL_ARB_PARK 0x0000000000200000UL /* PCI arbitration parking */
55 #define PSYCHO_PCICTRL_EEN 0x0000000000000100UL /* PCI Error Interrupt Enable */
57 #define PSYCHO_PCICTRL_AEN 0x000000000000003fUL /* PCI DVMA Arbitration Enable */
61 /* Helper function of IOMMU error checking, which checks out
[all …]
Dpci_sabre.c1 // SPDX-License-Identifier: GPL-2.0
2 /* pci_sabre.c: Sabre specific PCI controller support.
11 #include <linux/pci.h>
22 #include <asm/iommu.h>
34 /* SABRE PCI controller register offsets and definitions. */
36 #define SABRE_UEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */
37 #define SABRE_UEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */
38 #define SABRE_UEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */
39 #define SABRE_UEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */
47 #define SABRE_CEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */
[all …]
/linux-6.14.4/arch/x86/kernel/
Damd_gart_64.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Use the integrated AGP GART in the Hammer northbridge as an IOMMU for PCI.
6 * This allows to use PCI devices that only support 32bit addresses on systems
9 * See Documentation/core-api/dma-api-howto.rst for the interface specification.
23 #include <linux/pci.h>
29 #include <linux/iommu-helper.h>
34 #include <linux/dma-direct.h>
35 #include <linux/dma-map-ops.h>
38 #include <asm/iommu.h>
52 * If this is disabled the IOMMU will use an optimized flushing strategy
[all …]
Dpci-dma.c1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/dma-map-ops.h>
3 #include <linux/dma-direct.h>
4 #include <linux/iommu.h>
9 #include <linux/pci.h>
10 #include <linux/amd-iommu.h>
14 #include <asm/iommu.h>
19 #include <xen/swiotlb-xen.h>
37 /* Set this to 1 if there is a HW IOMMU in the system */
46 /* don't initialize swiotlb if iommu=off (no_iommu=1) */ in pci_swiotlb_detect()
[all …]
/linux-6.14.4/drivers/iommu/intel/
Dirq_remapping.c1 // SPDX-License-Identifier: GPL-2.0
3 #define pr_fmt(fmt) "DMAR-IR: " fmt
11 #include <linux/pci.h>
21 #include <asm/pci-direct.h>
24 #include "iommu.h"
26 #include "../iommu-pages.h"
29 struct intel_iommu *iommu; member
31 unsigned int bus; /* PCI bus number */
32 unsigned int devfn; /* PCI devfn number */
36 struct intel_iommu *iommu; member
[all …]
Dsvm.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/pci.h>
14 #include <linux/pci-ats.h>
22 #include "iommu.h"
25 #include "../iommu-pages.h"
28 void intel_svm_check(struct intel_iommu *iommu) in intel_svm_check() argument
30 if (!pasid_supported(iommu)) in intel_svm_check()
34 !cap_fl1gp_support(iommu->cap)) { in intel_svm_check()
36 iommu->name); in intel_svm_check()
41 !cap_fl5lp_support(iommu->cap)) { in intel_svm_check()
[all …]
Dnested.c1 // SPDX-License-Identifier: GPL-2.0
3 * nested.c - nested mode translation support
14 #include <linux/iommu.h>
15 #include <linux/pci.h>
16 #include <linux/pci-ats.h>
18 #include "iommu.h"
26 struct intel_iommu *iommu = info->iommu; in intel_nested_attach_dev() local
30 if (info->domain) in intel_nested_attach_dev()
33 if (iommu->agaw < dmar_domain->s2_domain->agaw) { in intel_nested_attach_dev()
35 return -ENODEV; in intel_nested_attach_dev()
[all …]
/linux-6.14.4/drivers/iommu/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 # The IOVA library may also be used by non-IOMMU_API users
15 bool "IOMMU Hardware Support"
26 menu "Generic IOMMU Pagetable Support"
40 sizes at both stage-1 and stage-2, as well as address spaces
41 up to 48-bits in size.
47 Enable self-tests for LPAE page table allocator. This performs
48 a series of page-table consistency checks during boot.
57 Enable support for the ARM Short-descriptor pagetable format.
58 This supports 32-bit virtual and physical addresses mapped using
[all …]
/linux-6.14.4/arch/arm64/boot/dts/apple/
Dt600x-die0.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 nco: clock-controller@28e03c000 {
11 compatible = "apple,t6000-nco", "apple,nco";
14 #clock-cells = <1>;
17 aic: interrupt-controller@28e100000 {
18 compatible = "apple,t6000-aic", "apple,aic2";
19 #interrupt-cells = <4>;
20 interrupt-controller;
23 reg-names = "core", "event";
24 power-domains = <&ps_aic>;
[all …]
/linux-6.14.4/arch/powerpc/platforms/cell/
Diommu.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * IOMMU implementation for Cell Broadband Processor Architecture
5 * (C) Copyright IBM Corporation 2006-2008
24 #include <asm/iommu.h>
26 #include <asm/pci-bridge.h>
29 #include <asm/cell-regs.h>
34 /* Define CELL_IOMMU_REAL_UNMAP to actually unmap non-used pages
43 * once spider-net has been fixed to pass the correct direction
89 #define IOSTE_PS_4K 0x0000000000000001ul /* - 4kB */
90 #define IOSTE_PS_64K 0x0000000000000003ul /* - 64kB */
[all …]
/linux-6.14.4/arch/powerpc/boot/dts/fsl/
Dp5020si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10000 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10000 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10000 0>;
51 compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
[all …]
Dp3041si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
[all …]

12345678910>>...15