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/linux-6.14.4/drivers/pci/controller/dwc/
Dpcie-designware-ep.c1 // SPDX-License-Identifier: GPL-2.0
14 #include "pcie-designware.h"
15 #include <linux/pci-epc.h>
16 #include <linux/pci-epf.h>
19 * dw_pcie_ep_get_func_from_ep - Get the struct dw_pcie_ep_func corresponding to
21 * @ep: DWC EP device
27 dw_pcie_ep_get_func_from_ep(struct dw_pcie_ep *ep, u8 func_no) in dw_pcie_ep_get_func_from_ep() argument
31 list_for_each_entry(ep_func, &ep->func_list, list) { in dw_pcie_ep_get_func_from_ep()
32 if (ep_func->func_no == func_no) in dw_pcie_ep_get_func_from_ep()
39 static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, u8 func_no, in __dw_pcie_ep_reset_bar() argument
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Dpci-exynos.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2020 Samsung Electronics Co., Ltd.
17 #include <linux/pci.h>
24 #include "pcie-designware.h"
26 #define to_exynos_pcie(x) dev_get_drvdata((x)->dev)
55 struct dw_pcie pci; member
72 static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie *ep, bool on) in exynos_pcie_sideband_dbi_w_mode() argument
76 val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_AWMISC); in exynos_pcie_sideband_dbi_w_mode()
81 exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_AWMISC); in exynos_pcie_sideband_dbi_w_mode()
84 static void exynos_pcie_sideband_dbi_r_mode(struct exynos_pcie *ep, bool on) in exynos_pcie_sideband_dbi_r_mode() argument
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Dpcie-designware.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 #include <linux/dma-mapping.h>
22 #include <linux/pci.h>
25 #include <linux/pci-epc.h>
26 #include <linux/pci-epf.h>
28 /* DWC PCIe IP-core versions (native support since v4.70a) */
38 ((_pci)->version _op DW_PCIE_VER_ ## _ver)
58 test_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps)
61 set_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps)
71 /* Synopsys-specific PCIe configuration registers */
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Dpci-layerscape-ep.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe controller EP driver for Freescale Layerscape SoCs
15 #include <linux/pci.h>
19 #include "pcie-designware.h"
35 #define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev)
44 struct dw_pcie *pci; member
54 struct dw_pcie *pci = pcie->pci; in ls_pcie_pf_lut_readl() local
56 if (pcie->big_endian) in ls_pcie_pf_lut_readl()
57 return ioread32be(pci->dbi_base + offset); in ls_pcie_pf_lut_readl()
59 return ioread32(pci->dbi_base + offset); in ls_pcie_pf_lut_readl()
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Dpcie-designware-plat.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
16 #include <linux/pci.h>
21 #include "pcie-designware.h"
24 struct dw_pcie *pci; member
35 static void dw_plat_pcie_ep_init(struct dw_pcie_ep *ep) in dw_plat_pcie_ep_init() argument
37 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); in dw_plat_pcie_ep_init() local
41 dw_pcie_ep_reset_bar(pci, bar); in dw_plat_pcie_ep_init()
44 static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, in dw_plat_pcie_ep_raise_irq() argument
47 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); in dw_plat_pcie_ep_raise_irq() local
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Dpcie-uniphier-ep.c1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/pci.h>
20 #include "pcie-designware.h"
74 struct dw_pcie pci; member
88 #define to_uniphier_pcie(x) dev_get_drvdata((x)->dev)
95 val = readl(priv->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
100 writel(val, priv->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
108 val = readl(priv->base + PCL_RSTCTRL2); in uniphier_pcie_phy_reset()
113 writel(val, priv->base + PCL_RSTCTRL2); in uniphier_pcie_phy_reset()
120 /* set EP mode */ in uniphier_pcie_pro5_init_ep()
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Dpcie-artpec6.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Axis ARTPEC-6 SoC
14 #include <linux/pci.h>
23 #include "pcie-designware.h"
25 #define to_artpec6_pcie(x) dev_get_drvdata((x)->dev)
33 struct dw_pcie *pci; member
34 struct regmap *regmap; /* DT axis,syscon-pcie */
47 /* ARTPEC-6 specific registers */
61 /* ARTPEC-7 specific fields */
66 /* ARTPEC-7 specific fields */
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Dpcie-dw-rockchip.c1 // SPDX-License-Identifier: GPL-2.0
6 * http://www.rock-chips.com
8 * Author: Simon Xue <xxm@rock-chips.com>
24 #include "pcie-designware.h"
34 #define to_rockchip_pcie(x) dev_get_drvdata((x)->dev)
58 struct dw_pcie pci; member
77 return readl_relaxed(rockchip->apb_base + reg); in rockchip_pcie_readl_apb()
83 writel_relaxed(val, rockchip->apb_base + reg); in rockchip_pcie_writel_apb()
97 generic_handle_domain_irq(rockchip->irq_domain, hwirq); in rockchip_pcie_intx_handler()
105 HIWORD_UPDATE_BIT(BIT(data->hwirq)), in rockchip_intx_mask()
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Dpcie-qcom-ep.c1 // SPDX-License-Identifier: GPL-2.0
26 #include "../../pci.h"
27 #include "pcie-designware.h"
28 #include "pcie-qcom-common.h"
153 #define to_pcie_ep(x) dev_get_drvdata((x)->dev)
163 * struct qcom_pcie_ep_cfg - Per SoC config struct
175 * struct qcom_pcie_ep - Qualcomm PCIe Endpoint Controller
176 * @pci: Designware PCIe controller struct
192 * @cfg: PCIe EP config struct
198 struct dw_pcie pci; member
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Dpci-dra7xx.c1 // SPDX-License-Identifier: GPL-2.0
3 * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
5 * Copyright (C) 2013-2014 Texas Instruments Incorporated - https://www.ti.com
22 #include <linux/pci.h>
32 #include "../../pci.h"
33 #include "pcie-designware.h"
89 struct dw_pcie *pci; member
91 int phy_count; /* DT phy-names count */
103 #define to_dra7xx_pcie(x) dev_get_drvdata((x)->dev)
107 return readl(pcie->base + offset); in dra7xx_pcie_readl()
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Dpcie-keembay.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include <linux/pci.h>
22 #include "pcie-designware.h"
59 struct dw_pcie pci; member
74 gpiod_set_value_cansleep(pcie->reset, 1); in keembay_ep_reset_assert()
83 * For more details, refer to PCI Express Card Electromechanical in keembay_ep_reset_deassert()
84 * Specification Revision 1.1, Table-2.4. in keembay_ep_reset_deassert()
88 gpiod_set_value_cansleep(pcie->reset, 0); in keembay_ep_reset_deassert()
96 val = readl(pcie->apb_base + PCIE_REGS_PCIE_APP_CNTRL); in keembay_pcie_ltssm_set()
101 writel(val, pcie->apb_base + PCIE_REGS_PCIE_APP_CNTRL); in keembay_pcie_ltssm_set()
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Dpcie-tegra194.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Copyright (C) 2019-2022 NVIDIA Corporation.
24 #include <linux/pci.h>
33 #include "pcie-designware.h"
35 #include <soc/tegra/bpmp-abi.h>
36 #include "../../pci.h"
248 struct dw_pcie pci; member
288 static inline struct tegra_pcie_dw *to_tegra_pcie(struct dw_pcie *pci) in to_tegra_pcie() argument
290 return container_of(pci, struct tegra_pcie_dw, pci); in to_tegra_pcie()
296 writel_relaxed(value, pcie->appl_base + reg); in appl_writel()
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PCIE_DW) += pcie-designware.o
3 obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
4 obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
5 obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
6 obj-$(CONFIG_PCIE_BT1) += pcie-bt1.o
7 obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
8 obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
9 obj-$(CONFIG_PCIE_FU740) += pcie-fu740.o
10 obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
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/linux-6.14.4/drivers/acpi/
Dviot.c1 // SPDX-License-Identifier: GPL-2.0
6 * para-virtual IOMMUs and the endpoints they manage. The OS uses it to
16 * hasn't yet been initialized, VIOT returns -EPROBE_DEFER to postpone probing
25 #include <linux/pci.h>
37 /* PCI range */
62 max_t(size_t, sizeof(*viot), viot->node_offset)); in viot_check_bounds()
63 end = ACPI_ADD_PTR(struct acpi_viot_header, viot, viot->header.length); in viot_check_bounds()
68 return -EOVERFLOW; in viot_check_bounds()
70 if (hdr->length < sizeof(*hdr)) { in viot_check_bounds()
72 return -EINVAL; in viot_check_bounds()
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/linux-6.14.4/drivers/video/fbdev/
Dsunxvr500.c1 /* sunxvr500.c: Sun 3DLABS XVR-500 Expert3D fb driver for sparc64 systems
11 #include <linux/pci.h>
17 /* XXX This device has a 'dev-comm' property which apparently is
22 * XXX as the values in the 'dev-comm' area are accurate then
56 static int e3d_get_props(struct e3d_info *ep) in e3d_get_props() argument
58 ep->width = of_getintprop_default(ep->of_node, "width", 0); in e3d_get_props()
59 ep->height = of_getintprop_default(ep->of_node, "height", 0); in e3d_get_props()
60 ep->depth = of_getintprop_default(ep->of_node, "depth", 8); in e3d_get_props()
62 if (!ep->width || !ep->height) { in e3d_get_props()
64 pci_name(ep->pdev)); in e3d_get_props()
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/linux-6.14.4/Documentation/PCI/endpoint/
Dpci-ntb-howto.rst1 .. SPDX-License-Identifier: GPL-2.0
4 PCI Non-Transparent Bridge (NTB) Endpoint Function (EPF) User Guide
9 This document is a guide to help users use pci-epf-ntb function driver
11 be followed in the host side and EP side is given below. For the hardware
13 Documentation/PCI/endpoint/pci-ntb-function.rst
19 ---------------------------
27 2900000.pcie-ep 2910000.pcie-ep
32 2900000.pcie-ep 2910000.pcie-ep
36 -------------------------
40 # ls /sys/bus/pci-epf/drivers
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Dpci-vntb-function.rst1 .. SPDX-License-Identifier: GPL-2.0
4 PCI vNTB Function
9 The difference between PCI NTB function and PCI vNTB function is
11 PCI NTB function need at two endpoint instances and connect HOST1
14 PCI vNTB function only use one host and one endpoint(EP), use NTB
15 connect EP and PCI host
17 .. code-block:: text
20 +------------+ +---------------------------------------+
22 +------------+ | +--------------+
25 +------------+ | +--------------+
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/linux-6.14.4/Documentation/devicetree/bindings/pci/
Dti,j721e-pci-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI J721E PCI EP (PCIe Wrapper)
11 - Kishon Vijay Abraham I <[email protected]>
16 - const: ti,j721e-pcie-ep
17 - const: ti,j784s4-pcie-ep
18 - description: PCIe EP controller in AM64
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Dsocionext,uniphier-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 PCI core. It shares common features with the PCIe DesignWare core and
13 Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml.
16 - Kunihiko Hayashi <[email protected]>
21 - socionext,uniphier-pro5-pcie-ep
22 - socionext,uniphier-nx1-pcie-ep
28 reg-names:
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Dfsl,imx6q-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lucas Stach <[email protected]>
11 - Richard Zhu <[email protected]>
15 thus inherits all the common properties defined in snps,dw-pcie-ep.yaml.
22 - fsl,imx8mm-pcie-ep
23 - fsl,imx8mq-pcie-ep
24 - fsl,imx8mp-pcie-ep
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Dti,am65-pci-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,am65-pci-ep.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI AM65 PCI Endpoint
11 - Kishon Vijay Abraham I <[email protected]>
14 - $ref: pci-ep.yaml#
19 - ti,am654-pcie-ep
24 reg-names:
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Dti-pci.txt1 TI PCI Controllers
4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
10 - phys : list of PHY specifiers (used by generic PHY framework)
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
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/linux-6.14.4/drivers/pci/controller/
Dpcie-rockchip-ep.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Simon Xue <xxm@rock-chips.com>
18 #include <linux/pci-epc.h>
20 #include <linux/pci-epf.h>
24 #include "pcie-rockchip.h"
27 * struct rockchip_pcie_ep - private data for PCIe endpoint controller driver
29 * @epc: PCI EPC device
40 * @irq_pci_fn: the latest PCI function that has updated the mapping of
45 * @link_up: True if the PCI link is up.
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/linux-6.14.4/drivers/pci/endpoint/
Dpci-epf-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Endpoint *Function* (EPF) library
10 #include <linux/dma-mapping.h>
14 #include <linux/pci-epc.h>
15 #include <linux/pci-epf.h>
16 #include <linux/pci-ep-cfs.h>
24 * pci_epf_unbind() - Notify the function driver that the binding between the
35 if (!epf->driver) { in pci_epf_unbind()
36 dev_WARN(&epf->dev, "epf device not bound to driver\n"); in pci_epf_unbind()
40 mutex_lock(&epf->lock); in pci_epf_unbind()
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/linux-6.14.4/drivers/net/ethernet/smsc/
Depic100.c3 Written/copyright 1997-2001 by Donald Becker.
13 SMC EtherPower II 9432 PCI adapter, and several CardBus cards.
22 [this link no longer provides anything useful -jgarzik]
24 ---------------------------------------------------------------------
32 /* The user-configurable values.
37 /* Used to pass the full-duplex flag, etc. */
39 static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
40 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
42 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
52 There are no ill effects from too-large receive rings. */
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