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/linux-6.14.4/Documentation/devicetree/bindings/pci/
Dnvidia,tegra194-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <[email protected]>
11 - Jon Hunter <[email protected]>
12 - Vidya Sagar <[email protected]>
16 inherits all the common properties defined in snps,dw-pcie-ep.yaml. Some
23 Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
29 - nvidia,tegra194-pcie-ep
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Dnvidia,tegra194-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <[email protected]>
11 - Jon Hunter <[email protected]>
12 - Vidya Sagar <[email protected]>
16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
20 See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device
26 - nvidia,tegra194-pcie
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Dsnps,dw-pcie-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <[email protected]>
11 - Gustavo Pimentel <[email protected]>
23 Interface - DBI. In accordance with the reference manual the register
24 configuration space belongs to the Configuration-Dependent Module (CDM)
25 and is split up into several sub-parts Standard PCIe configuration
26 space, Port Logic Registers (PL), Shadow Config-space Registers,
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/phy/
Dphy-tegra194-p2u.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-tegra194-p2u.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra194 & Tegra234 P2U
10 - Thierry Reding <[email protected]>
14 Speed) each interfacing with 12 and 8 P2U instances respectively.
16 each interfacing with 8, 8 and 8 P2U instances respectively.
17 A P2U instance is a glue logic between Synopsys DesignWare Core PCIe IP's PIPE
18 interface and PHY of HSIO/NVHS/GBE bricks. Each P2U instance represents one
[all …]
/linux-6.14.4/arch/arm64/boot/dts/nvidia/
Dtegra234-p3768-0000+p3767.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/input/linux-event-codes.h>
4 #include <dt-bindings/input/gpio-keys.h>
6 #include "tegra234-p3767.dtsi"
17 stdout-path = "serial0:115200n8";
20 bus@0 {
22 compatible = "nvidia,tegra194-hsuart";
23 reset-names = "serial";
28 compatible = "nvidia,tegra194-hsuart";
29 reset-names = "serial";
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Dtegra234-p3737-0000+p3701.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/input/linux-event-codes.h>
6 #include <dt-bindings/input/gpio-keys.h>
7 #include <dt-bindings/sound/rt5640.h>
17 stdout-path = "serial0:115200n8";
20 bus@0 {
27 dai-format = "i2s";
28 remote-endpoint = <&rt5640_ep>;
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Dtegra234-p3740-0002+p3701-0008.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/sound/rt5640.h>
7 #include "tegra234-p3701-0008.dtsi"
11 compatible = "nvidia,p3740-0002+p3701-0008", "nvidia,p3701-0008", "nvidia,tegra234";
19 stdout-path = "serial0:115200n8";
22 bus@0 {
29 dai-format = "i2s";
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Dtegra194-p2972-0000.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
7 #include "tegra194-p2888.dtsi"
11 compatible = "nvidia,p2972-0000", "nvidia,tegra194";
13 bus@0 {
24 #address-cells = <1>;
25 #size-cells = <0>;
27 port@0 {
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Dtegra194-p3509-0000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
8 bus@0 {
19 #address-cells = <1>;
20 #size-cells = <0>;
22 port@0 {
23 reg = <0>;
26 remote-endpoint = <&xbar_i2s3_ep>;
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Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
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Dtegra234.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
9 #include <dt-bindings/power/tegra234-powergate.h>
10 #include <dt-bindings/reset/tegra234-reset.h>
11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
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/linux-6.14.4/drivers/phy/tegra/
Dphy-tegra194-p2u.c1 // SPDX-License-Identifier: GPL-2.0+
3 * P2U (PIPE to UPHY) driver for Tegra T194 SoC
5 * Copyright (C) 2019-2022 NVIDIA Corporation.
17 #define P2U_CONTROL_CMN 0x74
21 #define P2U_PERIODIC_EQ_CTRL_GEN3 0xc0
22 #define P2U_PERIODIC_EQ_CTRL_GEN3_PERIODIC_EQ_EN BIT(0)
24 #define P2U_PERIODIC_EQ_CTRL_GEN4 0xc4
27 #define P2U_RX_DEBOUNCE_TIME 0xa4
28 #define P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_MASK 0xffff
31 #define P2U_DIR_SEARCH_CTRL 0xd4
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/linux-6.14.4/drivers/gpu/drm/ast/
Dast_dp501.c1 // SPDX-License-Identifier: GPL-2.0
20 release_firmware(ast->dp501_fw); in ast_release_firmware()
21 ast->dp501_fw = NULL; in ast_release_firmware()
26 struct drm_device *dev = &ast->base; in ast_load_dp501_microcode()
29 ret = request_firmware(&ast->dp501_fw, "ast_dp501_fw.bin", dev->dev); in ast_load_dp501_microcode()
33 return devm_add_action_or_reset(dev->dev, ast_release_firmware, ast); in ast_load_dp501_microcode()
39 sendack = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0x9b, 0xff); in send_ack()
40 sendack |= 0x80; in send_ack()
41 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x9b, 0x00, sendack); in send_ack()
47 sendack = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0x9b, 0xff); in send_nack()
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/linux-6.14.4/tools/perf/pmu-events/arch/x86/broadwellde/
Duncore-interconnect.json4 "Counter": "0,1",
5 "EventCode": "0x12",
9 "UMask": "0x1",
14 "Counter": "0,1",
15 "EventCode": "0x12",
19 "UMask": "0x2",
24 "Counter": "0,1",
32 "Counter": "0,1",
33 "EventCode": "0x13",
37 "UMask": "0x80",
[all …]
/linux-6.14.4/drivers/pci/controller/dwc/
Dpcie-tegra194.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Copyright (C) 2019-2022 NVIDIA Corporation.
33 #include "pcie-designware.h"
35 #include <soc/tegra/bpmp-abi.h>
38 #define TEGRA194_DWC_IP_VER 0x490A
39 #define TEGRA234_DWC_IP_VER 0x562A
41 #define APPL_PINMUX 0x0
42 #define APPL_PINMUX_PEX_RST BIT(0)
48 #define APPL_CTRL 0x4
52 #define APPL_CTRL_HW_HOT_RST_MODE_MASK GENMASK(1, 0)
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/linux-6.14.4/tools/perf/pmu-events/arch/x86/ivytown/
Duncore-interconnect.json4 "Counter": "0,1",
5 "EventCode": "0x17",
9 "UMask": "0x2",
14 "Counter": "0,1",
15 "EventCode": "0x17",
19 "UMask": "0x1",
24 "Counter": "0,1",
25 "EventCode": "0x14",
29 "UMask": "0x1",
34 "Counter": "0,1",
[all …]
/linux-6.14.4/tools/perf/pmu-events/arch/x86/haswellx/
Duncore-interconnect.json4 "Counter": "0,1,2,3",
7 …-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along wi…
9 "UMask": "0x4",
14 "Counter": "0,1,2,3",
17 …-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along wi…
19 "UMask": "0x2",
24 "Counter": "0,1",
25 "EventCode": "0x12",
29 "UMask": "0x1",
34 "Counter": "0,1",
[all …]
/linux-6.14.4/tools/perf/pmu-events/arch/x86/broadwellx/
Duncore-interconnect.json4 "Counter": "0,1,2,3",
7 …-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along wi…
9 "UMask": "0x4",
14 "Counter": "0,1,2,3",
17 …-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along wi…
19 "UMask": "0x2",
24 "Counter": "0,1",
25 "EventCode": "0x12",
29 "UMask": "0x1",
34 "Counter": "0,1",
[all …]