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/linux-6.14.4/drivers/nvmem/
Drockchip-otp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip OTP Driver
6 * Author: Finley Xiao <finley.xiao@rock-chips.com>
15 #include <linux/nvmem-provider.h>
22 /* OTP Register Offsets */
35 /* OTP Register bits and masks */
41 #define OTPC_SBPI_DONE BIT(1)
64 #define RK3588_BURST_NUM 1
68 #define RK3588_RD_DONE BIT(1)
85 static int rockchip_otp_reset(struct rockchip_otp *otp) in rockchip_otp_reset() argument
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Dlan9662-otpc.c1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/nvmem-provider.h>
18 #define OTP_OTP_FUNC_CMD_OTP_PROGRAM BIT(1)
27 #define OTP_OTP_STATUS_OTP_CPUMPEN BIT(1)
47 static int lan9662_otp_power(struct lan9662_otp *otp, bool up) in lan9662_otp_power() argument
49 void __iomem *pwrdn = OTP_OTP_PWR_DN(otp->base); in lan9662_otp_power()
53 if (lan9662_otp_wait_flag_clear(OTP_OTP_STATUS(otp->base), in lan9662_otp_power()
55 return -ETIMEDOUT; in lan9662_otp_power()
63 static int lan9662_otp_execute(struct lan9662_otp *otp) in lan9662_otp_execute() argument
65 if (lan9662_otp_wait_flag_clear(OTP_OTP_CMD_GO(otp->base), in lan9662_otp_execute()
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Dsunplus-ocotp.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/nvmem-provider.h>
21 * OTP memory
48 #define OTP_LOAD_SECURE_DATA BIT(1)
49 #define OTP_LOAD_SECURE_DATA_MASK ~BIT(1)
78 static int sp_otp_read_real(struct sp_ocotp_priv *otp, int addr, char *value) in sp_otp_read_real() argument
94 writel(readl(otp->base[OTPRX] + OTP_STATUS) & OTP_READ_DONE_MASK & in sp_otp_read_real()
95 OTP_LOAD_SECURE_DONE_MASK, otp->base[OTPRX] + OTP_STATUS); in sp_otp_read_real()
96 writel(addr, otp->base[OTPRX] + OTP_READ_ADDRESS); in sp_otp_read_real()
97 writel(readl(otp->base[OTPRX] + OTP_CONTROL_2) | OTP_READ, in sp_otp_read_real()
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Dmxs-ocotp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Freescale MXS On-Chip OTP driver
15 #include <linux/nvmem-provider.h>
37 static int mxs_ocotp_wait(struct mxs_ocotp *otp) in mxs_ocotp_wait() argument
42 while (timeout--) { in mxs_ocotp_wait()
43 status = readl(otp->base); in mxs_ocotp_wait()
52 return -EBUSY; in mxs_ocotp_wait()
54 return -EIO; in mxs_ocotp_wait()
62 struct mxs_ocotp *otp = context; in mxs_ocotp_read() local
66 ret = clk_enable(otp->clk); in mxs_ocotp_read()
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Dlpc18xx_otp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * NXP LPC18xx/43xx OTP memory NVMEM driver
10 * TODO: add support for writing OTP register via API in boot ROM.
15 #include <linux/nvmem-provider.h>
21 * LPC18xx OTP memory contains 4 banks with 4 32-bit words. Bank 0 starts
26 * Bank 1/2 is generale purpose or AES key storage for secure devices.
43 struct lpc18xx_otp *otp = context; in lpc18xx_otp_read() local
49 if (count > (LPC18XX_OTP_SIZE - index)) in lpc18xx_otp_read()
50 count = LPC18XX_OTP_SIZE - index; in lpc18xx_otp_read()
53 *buf++ = readl(otp->base + i * LPC18XX_OTP_WORD_SIZE); in lpc18xx_otp_read()
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Dstm32-romem.c1 // SPDX-License-Identifier: GPL-2.0
3 * STM32 Factory-programmed memory read access driver
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
9 #include <linux/arm-smccc.h>
12 #include <linux/nvmem-provider.h>
18 #include "stm32-bsec-optee-ta.h"
20 /* BSEC secure service access from non-secure */
51 *buf8++ = readb_relaxed(priv->base + i); in stm32_romem_read()
56 static int stm32_bsec_smc(u8 op, u32 otp, u32 data, u32 *result) in stm32_bsec_smc() argument
61 arm_smccc_smc(STM32_SMC_BSEC, op, otp, data, 0, 0, 0, 0, &res); in stm32_bsec_smc()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
38 calibration data required for the PCIe or the USB-C PHY.
41 be called nvmem-apple-efuses.
44 tristate "Broadcom On-Chip OTP Controller support"
49 Say y here to enable read/write access to the Broadcom OTP
53 will be called nvmem-bcm-ocotp.
73 will be called nvmem-imx-iim.
76 tristate "i.MX 6/7/8 On-Chip OTP Controller support"
80 This is a driver for the On-Chip OTP Controller (OCOTP) available on
81 i.MX6 SoCs, providing access to 4 Kbits of one-time programmable
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Dnintendo-otp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Nintendo Wii and Wii U OTP driver
5 * This is a driver exposing the OTP of a Nintendo Wii or Wii U console.
7 * This memory contains common and per-console keys, signatures and
10 * Based on reversed documentation from https://wiiubrew.org/wiki/Hardware/OTP
19 #include <linux/nvmem-provider.h>
39 .name = "wii-otp",
40 .num_banks = 1,
44 .name = "wiiu-otp",
56 while (words--) { in nintendo_otp_reg_read()
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Dimx-ocotp.c1 // SPDX-License-Identifier: GPL-2.0-only
14 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc
21 #include <linux/nvmem-provider.h>
28 * OTP Bank0 Word0
31 * of two consecutive OTP words.
106 void __iomem *base = priv->base; in imx_ocotp_wait_for_busy()
108 bm_ctrl_busy = priv->params->ctrl.bm_busy; in imx_ocotp_wait_for_busy()
109 bm_ctrl_error = priv->params->ctrl.bm_error; in imx_ocotp_wait_for_busy()
113 for (count = 10000; count >= 0; count--) { in imx_ocotp_wait_for_busy()
123 * - A write is performed to a shadow register during a shadow in imx_ocotp_wait_for_busy()
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Dstm32-bsec-optee-ta.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * OP-TEE STM32MP BSEC PTA interface, used by STM32 ROMEM driver
5 * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
10 #include "stm32-bsec-optee-ta.h"
13 * Read OTP memory
15 * [in] value[0].a OTP start offset in byte
16 * [in] value[0].b Access type (0:shadow, 1:fuse, 2:lock)
17 * [out] memref[1].buffer Output buffer to store read values
18 * [out] memref[1].size Size of OTP to be read
21 * TEE_SUCCESS - Invoke command success
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/linux-6.14.4/Documentation/devicetree/bindings/nvmem/
Drockchip,otp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/rockchip,otp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip internal OTP (One Time Programmable) memory
10 - Heiko Stuebner <[email protected]>
15 - rockchip,px30-otp
16 - rockchip,rk3308-otp
17 - rockchip,rk3588-otp
20 maxItems: 1
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Dlpc1850-otp.txt1 * NXP LPC18xx OTP memory
3 Internal OTP (One Time Programmable) memory for NXP LPC18xx/43xx devices.
6 - compatible: Should be "nxp,lpc1850-otp"
7 - reg: Must contain an entry with the physical base address and length
8 for each entry in reg-names.
9 - address-cells: must be set to 1.
10 - size-cells: must be set to 1.
15 otp: otp@40045000 {
16 compatible = "nxp,lpc1850-otp";
18 #address-cells = <1>;
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Dnintendo-otp.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/nvmem/nintendo-otp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Nintendo Wii and Wii U OTP
10 This binding represents the OTP memory as found on a Nintendo Wii or Wii U,
11 which contains common and per-console keys, signatures and related data
14 See https://wiiubrew.org/wiki/Hardware/OTP
17 - Emmanuel Gil Peyrot <[email protected]>
20 - $ref: nvmem.yaml#
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Dst,stm32-romem.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/st,stm32-romem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Factory-programmed data
10 This represents STM32 Factory-programmed read only non-volatile area: locked
11 flash, OTP, read-only HW regs... This contains various information such as:
16 - Fabrice Gasnier <[email protected]>
19 - $ref: nvmem.yaml#
20 - $ref: nvmem-deprecated-cells.yaml#
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/linux-6.14.4/drivers/net/wireless/mediatek/mt76/mt7615/
Deeprom.c1 // SPDX-License-Identifier: ISC
25 return -ETIMEDOUT; in mt7615_efuse_read()
50 if (is_mt7663(&dev->mt76)) in mt7615_efuse_init()
57 dev->mt76.otp.data = devm_kzalloc(dev->mt76.dev, len, GFP_KERNEL); in mt7615_efuse_init()
58 dev->mt76.otp.size = len; in mt7615_efuse_init()
59 if (!dev->mt76.otp.data) in mt7615_efuse_init()
60 return -ENOMEM; in mt7615_efuse_init()
62 buf = dev->mt76.otp.data; in mt7615_efuse_init()
80 ret = mt76_eeprom_init(&dev->mt76, MT7615_EEPROM_FULL_SIZE); in mt7615_eeprom_load()
89 u16 val = get_unaligned_le16(dev->eeprom.data); in mt7615_check_eeprom()
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/linux-6.14.4/Documentation/devicetree/bindings/mtd/
Dmtd.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <[email protected]>
11 - Richard Weinberger <[email protected]>
21 User-defined MTD device name. Can be used to assign user friendly
26 '#address-cells':
29 '#size-cells':
36 - compatible
39 "@[0-9a-f]+$":
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/linux-6.14.4/drivers/mtd/spi-nor/
Dotp.c1 // SPDX-License-Identifier: GPL-2.0
3 * OTP support for SPI NOR flashes
10 #include <linux/mtd/spi-nor.h>
14 #define spi_nor_otp_region_len(nor) ((nor)->params->otp.org->len)
15 #define spi_nor_otp_n_regions(nor) ((nor)->params->otp.org->n_regions)
18 * spi_nor_otp_read_secr() - read security register
27 * an one-time-programmable memory area, consisting of multiple bytes (usually
28 * 256). Thus one "security register" maps to one OTP region.
34 * Return: number of bytes read successfully, -errno otherwise
43 read_opcode = nor->read_opcode; in spi_nor_otp_read_secr()
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Dcore.h1 /* SPDX-License-Identifier: GPL-2.0 */
18 #define SPI_NOR_DEFAULT_N_BANKS 1
44 SPI_MEM_OP_DATA_IN(1, buf, 0))
56 SPI_MEM_OP_DATA_OUT(1, buf, 0))
62 SPI_MEM_OP_DATA_OUT(1, buf, 0))
68 SPI_MEM_OP_DATA_IN(1, buf, 0))
80 SPI_MEM_OP_DATA_OUT(1, buf, 0))
103 SPI_MEM_OP_DUMMY(1, 0), \
127 SNOR_F_NO_OP_CHIP_ERASE = BIT(1),
203 * struct spi_nor_erase_type - Structure to describe a SPI NOR erase type
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/linux-6.14.4/include/linux/mfd/wm831x/
Dotp.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * include/linux/mfd/wm831x/otp.h -- OTP interface for WM831x
17 * R30720 (0x7800) - Unique ID 1
19 #define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
20 #define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
21 #define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
24 * R30721 (0x7801) - Unique ID 2
26 #define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
27 #define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
28 #define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
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/linux-6.14.4/drivers/net/wireless/mediatek/mt76/mt7603/
Deeprom.c1 // SPDX-License-Identifier: ISC
21 return -ETIMEDOUT; in mt7603_efuse_read()
51 dev->mt76.otp.data = devm_kzalloc(dev->mt76.dev, len, GFP_KERNEL); in mt7603_efuse_init()
52 dev->mt76.otp.size = len; in mt7603_efuse_init()
53 if (!dev->mt76.otp.data) in mt7603_efuse_init()
54 return -ENOMEM; in mt7603_efuse_init()
56 buf = dev->mt76.otp.data; in mt7603_efuse_init()
100 MT_EE_TX_POWER_0_START_2G + 1, in mt7603_apply_cal_free_data()
102 MT_EE_TX_POWER_1_START_2G + 1, in mt7603_apply_cal_free_data()
104 struct device_node *np = dev->mt76.dev->of_node; in mt7603_apply_cal_free_data()
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/linux-6.14.4/drivers/crypto/
Datmel-sha204a.c1 // SPDX-License-Identifier: GPL-2.0
19 #include "atmel-i2c.h"
24 struct atmel_i2c_client_priv *i2c_priv = work_data->ctx; in atmel_sha204a_rng_done()
28 dev_warn_ratelimited(&i2c_priv->client->dev, in atmel_sha204a_rng_done()
32 rng->priv = (unsigned long)work_data; in atmel_sha204a_rng_done()
33 atomic_dec(&i2c_priv->tfm_count); in atmel_sha204a_rng_done()
44 /* keep maximum 1 asynchronous read in flight at any time */ in atmel_sha204a_rng_read_nonblocking()
45 if (!atomic_add_unless(&i2c_priv->tfm_count, 1, 1)) in atmel_sha204a_rng_read_nonblocking()
48 if (rng->priv) { in atmel_sha204a_rng_read_nonblocking()
49 work_data = (struct atmel_i2c_work_data *)rng->priv; in atmel_sha204a_rng_read_nonblocking()
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/linux-6.14.4/drivers/net/wireless/intel/iwlwifi/dvm/
Deeprom.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2005-2014, 2018-2019, 2021, 2024 Intel Corporation
9 #include "iwl-drv.h"
10 #include "iwl-debug.h"
11 #include "iwl-io.h"
12 #include "iwl-prph.h"
13 #include "iwl-csr.h"
46 #define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */
77 #define EEPROM_RF_CFG_TYPE_MSK(x) (x & 0x3) /* bits 0-1 */
78 #define EEPROM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */
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/linux-6.14.4/drivers/mtd/nand/onenand/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
16 from 1 to 0. There is a rare possibility that even though the
45 bool "OneNAND OTP Support"
48 a One-Time Programmable Block memory area.
49 Also, 1st Block of NAND Flash Array can be used as OTP.
51 The OTP block can be read, programmed and locked using the same
53 OTP block cannot be erased.
55 OTP block is fully-guaranteed to be a valid block.
61 Since the device is equipped with two DataRAMs, and two-plane NAND
/linux-6.14.4/drivers/net/wireless/broadcom/brcm80211/brcmfmac/
Dpcie.c1 // SPDX-License-Identifier: ISC
52 BRCMF_FW_DEF(43602, "brcmfmac43602-pcie");
53 BRCMF_FW_DEF(4350, "brcmfmac4350-pcie");
54 BRCMF_FW_DEF(4350C, "brcmfmac4350c2-pcie");
55 BRCMF_FW_CLM_DEF(4355, "brcmfmac4355-pcie");
56 BRCMF_FW_CLM_DEF(4355C1, "brcmfmac4355c1-pcie");
57 BRCMF_FW_CLM_DEF(4356, "brcmfmac4356-pcie");
58 BRCMF_FW_CLM_DEF(43570, "brcmfmac43570-pcie");
59 BRCMF_FW_DEF(4358, "brcmfmac4358-pcie");
60 BRCMF_FW_DEF(4359, "brcmfmac4359-pcie");
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/linux-6.14.4/drivers/net/wireless/intel/iwlwifi/
Diwl-agn-hw.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2005-2014 Intel Corporation
6 * Please use this file (iwl-agn-hw.h) only for hardware-related definitions.
18 #define IWLAGN_RTC_INST_SIZE (IWLAGN_RTC_INST_UPPER_BOUND - \
20 #define IWLAGN_RTC_DATA_SIZE (IWLAGN_RTC_DATA_UPPER_BOUND - \
28 (IWL60_RTC_INST_UPPER_BOUND - IWL60_RTC_INST_LOWER_BOUND)
30 (IWL60_RTC_DATA_UPPER_BOUND - IWL60_RTC_DATA_LOWER_BOUND)
42 #define IWLAGN_TX_POWER_TARGET_POWER_MIN (0) /* 0 dBm: 1 milliwatt */
51 #define OTP_MAX_LL_ITEMS_1000 (3) /* OTP blocks for 1000 */
52 #define OTP_MAX_LL_ITEMS_6x00 (4) /* OTP blocks for 6x00 */
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