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/aosp_15_r20/external/elfutils/tests/
H A Drun-show-die-info.sh28 Offset : 11
29 CU offset : 11
38 Offset : 104
39 CU offset : 104
45 Offset : 127
46 CU offset : 127
52 Offset : 146
53 CU offset : 11
62 Offset : 239
63 CU offset : 104
[all …]
H A Drun-show-abbrev.sh25 abbrev[0]: attr[0]: code = 16, form = 6, offset = 0
26 abbrev[0]: attr[1]: code = 18, form = 1, offset = 2
27 abbrev[0]: attr[2]: code = 17, form = 1, offset = 4
28 abbrev[0]: attr[3]: code = 3, form = 8, offset = 6
29 abbrev[0]: attr[4]: code = 27, form = 8, offset = 8
30 abbrev[0]: attr[5]: code = 37, form = 8, offset = 10
31 abbrev[0]: attr[6]: code = 19, form = 11, offset = 12
33 abbrev[19]: attr[0]: code = 1, form = 19, offset = 19
34 abbrev[19]: attr[1]: code = 63, form = 12, offset = 21
35 abbrev[19]: attr[2]: code = 3, form = 8, offset = 23
[all …]
/aosp_15_r20/external/mesa3d/src/intel/vulkan/grl/gpu/libs/
H A Dlsc_intrinsics_fallback.cl10 uint load_uchar_to_uint_L1UC_L3UC(global uchar* it, int offset)
12 return (uint)(it[offset]);
15 uint load_uchar_to_uint_L1UC_L3C(global uchar* it, int offset)
17 return (uint)(it[offset]);
20 uint load_uchar_to_uint_L1C_L3UC(global uchar* it, int offset)
22 return (uint)(it[offset]);
25 uint load_uchar_to_uint_L1C_L3C(global uchar* it, int offset)
27 return (uint)(it[offset]);
30 uint load_uchar_to_uint_L1S_L3UC(global uchar* it, int offset)
32 return (uint)(it[offset]);
[all …]
H A Dlsc_intrinsics.cl143 uint load_uchar_to_uint_L1UC_L3UC(global uchar* it, int offset)
145 return __builtin_IB_lsc_load_global_uchar_to_uint(it, offset, LSC_LDCC_L1UC_L3UC);
148 uint load_uchar_to_uint_L1UC_L3C(global uchar* it, int offset)
150 return __builtin_IB_lsc_load_global_uchar_to_uint(it, offset, LSC_LDCC_L1UC_L3C);
153 uint load_uchar_to_uint_L1C_L3UC(global uchar* it, int offset)
155 return __builtin_IB_lsc_load_global_uchar_to_uint(it, offset, LSC_LDCC_L1C_L3UC);
158 uint load_uchar_to_uint_L1C_L3C(global uchar* it, int offset)
160 return __builtin_IB_lsc_load_global_uchar_to_uint(it, offset, LSC_LDCC_L1C_L3C);
163 uint load_uchar_to_uint_L1S_L3UC(global uchar* it, int offset)
165 return __builtin_IB_lsc_load_global_uchar_to_uint(it, offset, LSC_LDCC_L1S_L3UC);
[all …]
H A Dlsc_intrinsics.h9 uint load_uchar_to_uint_L1UC_L3UC(global uchar* it, int offset);
10 uint load_uchar_to_uint_L1UC_L3C(global uchar* it, int offset);
11 uint load_uchar_to_uint_L1C_L3UC(global uchar* it, int offset);
12 uint load_uchar_to_uint_L1C_L3C(global uchar* it, int offset);
13 uint load_uchar_to_uint_L1S_L3UC(global uchar* it, int offset);
14 uint load_uchar_to_uint_L1S_L3C(global uchar* it, int offset);
15 uint load_uchar_to_uint_L1IAR_L3C(global uchar* it, int offset);
17 uint load_ushort_to_uint_L1UC_L3UC(global ushort* it, int offset);
18 uint load_ushort_to_uint_L1UC_L3C(global ushort* it, int offset);
19 uint load_ushort_to_uint_L1C_L3UC(global ushort* it, int offset);
[all …]
/aosp_15_r20/external/mesa3d/src/freedreno/fdl/
H A Dfd6_layout_test.c26 {.offset = 0, .pitch = 256},
27 {.offset = 8192, .pitch = 256},
28 {.offset = 12288, .pitch = 256},
29 {.offset = 14336, .pitch = 256},
30 {.offset = 15360, .pitch = 256},
31 {.offset = 15872, .pitch = 256},
49 {.offset = 0, .pitch = 4096},
50 {.offset = 65536, .pitch = 2048},
51 {.offset = 98304, .pitch = 1024},
52 {.offset = 114688, .pitch = 512},
[all …]
/aosp_15_r20/external/mesa3d/src/freedreno/registers/adreno/
H A Da5xx.xml862 <reg32 offset="0x0800" name="CP_RB_BASE"/>
863 <reg32 offset="0x0801" name="CP_RB_BASE_HI"/>
864 <reg32 offset="0x0802" name="CP_RB_CNTL"/>
865 <reg32 offset="0x0804" name="CP_RB_RPTR_ADDR"/>
866 <reg32 offset="0x0805" name="CP_RB_RPTR_ADDR_HI"/>
867 <reg32 offset="0x0806" name="CP_RB_RPTR"/>
868 <reg32 offset="0x0807" name="CP_RB_WPTR"/>
869 <reg32 offset="0x0808" name="CP_PFP_STAT_ADDR"/>
870 <reg32 offset="0x0809" name="CP_PFP_STAT_DATA"/>
871 <reg32 offset="0x080b" name="CP_DRAW_STATE_ADDR"/>
[all …]
H A Da4xx.xml865 <reg32 offset="0x0cc0" name="RB_GMEM_BASE_ADDR"/>
866 <reg32 offset="0x0cc7" name="RB_PERFCTR_RB_SEL_0" type="a4xx_rb_perfcounter_select"/>
867 <reg32 offset="0x0cc8" name="RB_PERFCTR_RB_SEL_1" type="a4xx_rb_perfcounter_select"/>
868 <reg32 offset="0x0cc9" name="RB_PERFCTR_RB_SEL_2" type="a4xx_rb_perfcounter_select"/>
869 <reg32 offset="0x0cca" name="RB_PERFCTR_RB_SEL_3" type="a4xx_rb_perfcounter_select"/>
870 <reg32 offset="0x0ccb" name="RB_PERFCTR_RB_SEL_4" type="a4xx_rb_perfcounter_select"/>
871 <reg32 offset="0x0ccc" name="RB_PERFCTR_RB_SEL_5" type="a4xx_rb_perfcounter_select"/>
872 <reg32 offset="0x0ccd" name="RB_PERFCTR_RB_SEL_6" type="a4xx_rb_perfcounter_select"/>
873 <reg32 offset="0x0cce" name="RB_PERFCTR_RB_SEL_7" type="a4xx_rb_perfcounter_select"/>
874 <reg32 offset="0x0ccf" name="RB_PERFCTR_CCU_SEL_0" type="a4xx_ccu_perfcounter_select"/>
[all …]
/aosp_15_r20/external/tpm2-tss/include/tss2/
H A Dtss2_mu.h28 size_t *offset);
34 size_t *offset,
42 size_t *offset);
48 size_t *offset,
56 size_t *offset);
62 size_t *offset,
70 size_t *offset);
76 size_t *offset,
84 size_t *offset);
90 size_t *offset,
[all …]
/aosp_15_r20/frameworks/libs/native_bridge_support/android_api/libvulkan/proxy/
Dapi_x86.json4725 "offset" : 0, number
4730 "offset" : 256, number
4735 "offset" : 288, number
4740 "offset" : 320, number
4745 "offset" : 352, number
4750 "offset" : 384, number
4755 "offset" : 416, number
4760 "offset" : 544, number
4765 "offset" : 576, number
4770 "offset" : 608, number
[all …]
Dapi_arm.json4926 "offset" : 0, number
4931 "offset" : 256, number
4936 "offset" : 288, number
4941 "offset" : 320, number
4946 "offset" : 352, number
4951 "offset" : 384, number
4956 "offset" : 416, number
4961 "offset" : 544, number
4966 "offset" : 576, number
4971 "offset" : 608, number
[all …]
Dapi_x86_64.json4737 "offset" : 0, number
4742 "offset" : 448, number
4747 "offset" : 480, number
4752 "offset" : 512, number
4757 "offset" : 544, number
4762 "offset" : 576, number
4767 "offset" : 640, number
4772 "offset" : 896, number
4777 "offset" : 960, number
4782 "offset" : 1024, number
[all …]
Dapi_arm64.json4701 "offset" : 0, number
4706 "offset" : 448, number
4711 "offset" : 480, number
4716 "offset" : 512, number
4721 "offset" : 544, number
4726 "offset" : 576, number
4731 "offset" : 640, number
4736 "offset" : 896, number
4741 "offset" : 960, number
4746 "offset" : 1024, number
[all …]
Dapi_riscv64.json4701 "offset" : 0, number
4706 "offset" : 448, number
4711 "offset" : 480, number
4716 "offset" : 512, number
4721 "offset" : 544, number
4726 "offset" : 576, number
4731 "offset" : 640, number
4736 "offset" : 896, number
4741 "offset" : 960, number
4746 "offset" : 1024, number
[all …]
/aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/raptorlake/
H A DFspmUpd.h58 /** Offset 0x0040 - Platform Reserved Memory Size
63 /** Offset 0x0048 - SPD Data Length
69 /** Offset 0x004A - Enable above 4GB MMIO resource support
75 /** Offset 0x004B - Enable/Disable CrashLog Device 10
81 /** Offset 0x004C - Memory SPD Pointer Controller 0 Channel 0 Dimm 0
86 /** Offset 0x0050 - Memory SPD Pointer Controller 0 Channel 0 Dimm 1
91 /** Offset 0x0054 - Memory SPD Pointer Controller 0 Channel 1 Dimm 0
96 /** Offset 0x0058 - Memory SPD Pointer Controller 0 Channel 1 Dimm 1
101 /** Offset 0x005C - Memory SPD Pointer Controller 0 Channel 2 Dimm 0
106 /** Offset 0x0060 - Memory SPD Pointer Controller 0 Channel 2 Dimm 1
[all …]
H A DFspsUpd.h88 /** Offset 0x0040 - Logo Pointer
93 /** Offset 0x0044 - Logo Size
98 /** Offset 0x0048 - Blt Buffer Address
103 /** Offset 0x004C - Blt Buffer Size
109 /** Offset 0x0050 - Graphics Configuration Ptr
114 /** Offset 0x0054 - Enable Device 4
120 /** Offset 0x0055 - Show SPI controller
126 /** Offset 0x0056
130 /** Offset 0x0058 - MicrocodeRegionBase
135 /** Offset 0x005C - MicrocodeRegionSize
[all …]
/aosp_15_r20/external/vixl/test/aarch32/
H A Dtest-assembler-cond-rd-memop-immediate-512-a32.cc73 int32_t offset; member
100 const TestData kTests[] = {{{pl, r13, r0, plus, 0, Offset},
103 "pl r13 r0 plus 0 Offset",
105 {{ge, r5, r3, plus, 0, Offset},
108 "ge r5 r3 plus 0 Offset",
110 {{cc, r0, r4, plus, 0, Offset},
113 "cc r0 r4 plus 0 Offset",
115 {{ge, r0, r0, plus, 0, Offset},
118 "ge r0 r0 plus 0 Offset",
120 {{eq, r12, r3, plus, 0, Offset},
[all …]
H A Dtest-assembler-cond-rd-memop-immediate-8192-a32.cc73 int32_t offset; member
100 const TestData kTests[] = {{{pl, r13, r0, plus, 0, Offset},
103 "pl r13 r0 plus 0 Offset",
105 {{ge, r5, r3, plus, 0, Offset},
108 "ge r5 r3 plus 0 Offset",
110 {{cc, r0, r4, plus, 0, Offset},
113 "cc r0 r4 plus 0 Offset",
115 {{ge, r0, r0, plus, 0, Offset},
118 "ge r0 r0 plus 0 Offset",
120 {{eq, r12, r3, plus, 0, Offset},
[all …]
H A Dtest-assembler-cond-rd-memop-rs-a32.cc104 const TestData kTests[] = {{{pl, r8, r11, plus, r6, Offset},
107 "pl r8 r11 plus r6 Offset",
109 {{le, r4, r8, plus, r5, Offset},
112 "le r4 r8 plus r5 Offset",
114 {{vs, r2, r6, plus, r14, Offset},
117 "vs r2 r6 plus r14 Offset",
119 {{ls, r1, r7, plus, r8, Offset},
122 "ls r1 r7 plus r8 Offset",
124 {{ge, r14, r6, plus, r14, Offset},
127 "ge r14 r6 plus r14 Offset",
[all …]
/aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_32/
H A DFspmUpd.h58 /** Offset 0x0040 - Platform Reserved Memory Size
63 /** Offset 0x0048 - SPD Data Length
69 /** Offset 0x004A - Enable above 4GB MMIO resource support
75 /** Offset 0x004B - Reserved
79 /** Offset 0x004C - Memory SPD Pointer Controller 0 Channel 0 Dimm 0
84 /** Offset 0x0050 - Memory SPD Pointer Controller 0 Channel 0 Dimm 1
89 /** Offset 0x0054 - Memory SPD Pointer Controller 0 Channel 1 Dimm 0
94 /** Offset 0x0058 - Memory SPD Pointer Controller 0 Channel 1 Dimm 1
99 /** Offset 0x005C - Memory SPD Pointer Controller 0 Channel 2 Dimm 0
104 /** Offset 0x0060 - Memory SPD Pointer Controller 0 Channel 2 Dimm 1
[all …]
/aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/meteorlake/x86_64/
H A DFspmUpd.h58 /** Offset 0x0060 - Platform Reserved Memory Size
63 /** Offset 0x0068 - SPD Data Length
69 /** Offset 0x006A - Enable above 4GB MMIO resource support
75 /** Offset 0x006B - Reserved
79 /** Offset 0x0070 - Memory SPD Pointer Controller 0 Channel 0 Dimm 0
84 /** Offset 0x0078 - Memory SPD Pointer Controller 0 Channel 0 Dimm 1
89 /** Offset 0x0080 - Memory SPD Pointer Controller 0 Channel 1 Dimm 0
94 /** Offset 0x0088 - Memory SPD Pointer Controller 0 Channel 1 Dimm 1
99 /** Offset 0x0090 - Memory SPD Pointer Controller 0 Channel 2 Dimm 0
104 /** Offset 0x0098 - Memory SPD Pointer Controller 0 Channel 2 Dimm 1
[all …]
/aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/twinlake/
H A DFspmUpd.h58 /** Offset 0x0040 - Platform Reserved Memory Size
63 /** Offset 0x0048 - SPD Data Length
69 /** Offset 0x004A - Enable above 4GB MMIO resource support
75 /** Offset 0x004B - Enable/Disable CrashLog Device 10
81 /** Offset 0x004C - Memory SPD Pointer Controller 0 Channel 0 Dimm 0
86 /** Offset 0x0050 - Memory SPD Pointer Controller 0 Channel 0 Dimm 1
91 /** Offset 0x0054 - Memory SPD Pointer Controller 0 Channel 1 Dimm 0
96 /** Offset 0x0058 - Memory SPD Pointer Controller 0 Channel 1 Dimm 1
101 /** Offset 0x005C - Memory SPD Pointer Controller 0 Channel 2 Dimm 0
106 /** Offset 0x0060 - Memory SPD Pointer Controller 0 Channel 2 Dimm 1
[all …]
/aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/alderlake_n/
H A DFspmUpd.h58 /** Offset 0x0040 - Platform Reserved Memory Size
63 /** Offset 0x0048 - SPD Data Length
69 /** Offset 0x004A - Enable above 4GB MMIO resource support
75 /** Offset 0x004B - Enable/Disable CrashLog Device 10
81 /** Offset 0x004C - Memory SPD Pointer Controller 0 Channel 0 Dimm 0
86 /** Offset 0x0050 - Memory SPD Pointer Controller 0 Channel 0 Dimm 1
91 /** Offset 0x0054 - Memory SPD Pointer Controller 0 Channel 1 Dimm 0
96 /** Offset 0x0058 - Memory SPD Pointer Controller 0 Channel 1 Dimm 1
101 /** Offset 0x005C - Memory SPD Pointer Controller 0 Channel 2 Dimm 0
106 /** Offset 0x0060 - Memory SPD Pointer Controller 0 Channel 2 Dimm 1
[all …]
/aosp_15_r20/external/coreboot/src/vendorcode/intel/fsp/fsp2_0/alderlake/
H A DFspmUpd.h58 /** Offset 0x0040 - Platform Reserved Memory Size
63 /** Offset 0x0048 - SPD Data Length
69 /** Offset 0x004A - Enable above 4GB MMIO resource support
75 /** Offset 0x004B - Enable/Disable CrashLog Device 10
81 /** Offset 0x004C - Memory SPD Pointer Controller 0 Channel 0 Dimm 0
86 /** Offset 0x0050 - Memory SPD Pointer Controller 0 Channel 0 Dimm 1
91 /** Offset 0x0054 - Memory SPD Pointer Controller 0 Channel 1 Dimm 0
96 /** Offset 0x0058 - Memory SPD Pointer Controller 0 Channel 1 Dimm 1
101 /** Offset 0x005C - Memory SPD Pointer Controller 0 Channel 2 Dimm 0
106 /** Offset 0x0060 - Memory SPD Pointer Controller 0 Channel 2 Dimm 1
[all …]
/aosp_15_r20/external/flatbuffers/tests/ts/ts-flat-files/
H A Dmonster_test_generated.ts159 static createUnused(builder:flatbuffers.Builder, a: number):flatbuffers.Offset {
162 return builder.offset();
186 const offset = this.bb!.__offset(this.bb_pos, 4); constant
187 …return offset ? (obj || new TableA()).__init(this.bb!.__indirect(this.bb_pos + offset), this.bb!) …
194 static addA(builder:flatbuffers.Builder, aOffset:flatbuffers.Offset) {
198 static endTableB(builder:flatbuffers.Builder):flatbuffers.Offset {
199 const offset = builder.endObject(); constant
200 return offset;
203 static createTableB(builder:flatbuffers.Builder, aOffset:flatbuffers.Offset):flatbuffers.Offset {
237 const offset = this.bb!.__offset(this.bb_pos, 4); constant
[all …]

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