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/linux-6.14.4/Documentation/devicetree/bindings/pci/
Dsamsung,exynos-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/samsung,exynos-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Szyprowski <[email protected]>
11 - Jaehoon Chung <[email protected]>
16 snps,dw-pcie.yaml.
19 - $ref: /schemas/pci/snps,dw-pcie.yaml#
23 const: samsung,exynos5433-pcie
27 - description: Data Bus Interface (DBI) registers.
[all …]
Dti,am65-pci-host.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,am65-pci-host.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <[email protected]>
14 - $ref: /schemas/pci/pci-host-bridge.yaml#
19 - ti,am654-pcie-rc
20 - ti,keystone-pcie
25 reg-names:
[all …]
Dsocionext,uniphier-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
16 - Kunihiko Hayashi <[email protected]>
19 - $ref: /schemas/pci/snps,dw-pcie.yaml#
24 - socionext,uniphier-pcie
30 reg-names:
33 - const: dbi
[all …]
Dsnps,dw-pcie-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <[email protected]>
11 - Gustavo Pimentel <[email protected]>
23 Interface - DBI. In accordance with the reference manual the register
24 configuration space belongs to the Configuration-Dependent Module (CDM)
25 and is split up into several sub-parts Standard PCIe configuration
26 space, Port Logic Registers (PL), Shadow Config-space Registers,
[all …]
Dtoshiba,visconti-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/toshiba,visconti-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nobuhiro Iwamatsu <[email protected]>
16 - $ref: /schemas/pci/snps,dw-pcie.yaml#
20 const: toshiba,visconti-pcie
24 - description: Data Bus Interface (DBI) registers.
25 - description: PCIe configuration space region.
26 - description: Visconti specific additional registers.
[all …]
Dsnps,dw-pcie.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <[email protected]>
11 - Gustavo Pimentel <[email protected]>
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie
23 - compatible
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Dfsl,layerscape-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <[email protected]>
16 which is used to describe the PLL settings at the time of chip-reset.
26 - enum:
27 - fsl,ls1012a-pcie
28 - fsl,ls1021a-pcie
29 - fsl,ls1028a-pcie
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Dnvidia,tegra194-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <[email protected]>
11 - Jon Hunter <[email protected]>
12 - Vidya Sagar <[email protected]>
16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
20 See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device
26 - nvidia,tegra194-pcie
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/linux-6.14.4/arch/arm64/boot/dts/marvell/
Dcn9132-db.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Device tree for the CN9132-DB board.
8 #include "cn9131-db.dtsi"
12 "marvell,armada-ap807-quad", "marvell,armada-ap807";
20 cp2_reg_usb3_vbus0: regulator-7 {
21 compatible = "regulator-fixed";
22 regulator-name = "cp2-xhci0-vbus";
23 regulator-min-microvolt = <5000000>;
24 regulator-max-microvolt = <5000000>;
25 enable-active-high;
[all …]
Dcn9130-crb-A.dts1 // SPDX-License-Identifier: GPL-2.0+
6 #include "cn9130-crb.dtsi"
9 model = "Marvell Armada CN9130-CRB-A";
14 num-lanes = <4>;
15 num-viewport = <8>;
21 iommu-map =
25 iommu-map-mask = <0x031f>;
30 usb-phy = <&cp0_usb3_0_phy0>;
31 phy-names = "usb";
36 usb-phy = <&cp0_usb3_0_phy1>;
[all …]
Dcn9130-crb-B.dts1 // SPDX-License-Identifier: GPL-2.0+
6 #include "cn9130-crb.dtsi"
9 model = "Marvell Armada CN9130-CRB-B";
14 num-lanes = <1>;
15 num-viewport = <8>;
18 iommu-map =
22 iommu-map-mask = <0x031f>;
27 sata-port@0 {
37 usb-phy = <&cp0_usb3_0_phy0>;
38 phy-names = "usb";
[all …]
Dcn9131-db.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Device tree for the CN9131-DB board.
8 #include "cn9130-db.dtsi"
12 "marvell,armada-ap807-quad", "marvell,armada-ap807";
21 cp1_reg_usb3_vbus0: regulator-6 {
22 compatible = "regulator-fixed";
23 pinctrl-names = "default";
24 pinctrl-0 = <&cp1_xhci0_vbus_pins>;
25 regulator-name = "cp1-xhci0-vbus";
26 regulator-min-microvolt = <5000000>;
[all …]
Darmada-8040-mcbin.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-8040.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
14 compatible = "marvell,armada8040-mcbin", "marvell,armada8040",
15 "marvell,armada-ap806-quad", "marvell,armada-ap806";
18 stdout-path = "serial0:115200n8";
34 v_3_3: regulator-3-3v {
35 compatible = "regulator-fixed";
36 regulator-name = "v_3_3";
37 regulator-min-microvolt = <3300000>;
[all …]
Dcn9130-db.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Device tree for the CN9130-DB board.
10 #include <dt-bindings/gpio/gpio.h>
14 stdout-path = "serial0:115200n8";
33 ap0_reg_sd_vccq: regulator-1 {
34 compatible = "regulator-gpio";
35 regulator-name = "ap0_sd_vccq";
36 regulator-min-microvolt = <1800000>;
37 regulator-max-microvolt = <3300000>;
42 cp0_reg_usb3_vbus0: regulator-2 {
[all …]
/linux-6.14.4/arch/arm64/boot/dts/freescale/
Dimx8qm-ss-hsio.dtsi1 // SPDX-License-Identifier: GPL-2.0+
8 compatible = "simple-bus";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 compatible = "fsl,imx8q-pcie";
19 reg-names = "dbi", "config";
22 #interrupt-cells = <1>;
24 interrupt-names = "msi";
25 #address-cells = <3>;
26 #size-cells = <2>;
[all …]
Dimx8-ss-hsio.dtsi1 // SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/phy/phy.h>
9 hsio_axi_clk: clock-hsio-axi {
10 compatible = "fixed-clock";
11 #clock-cells = <0>;
12 clock-frequency = <400000000>;
13 clock-output-names = "hsio_axi_clk";
16 hsio_per_clk: clock-hsio-per {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
[all …]
Dfsl-ls1046a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1046A family SoC.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
37 #address-cells = <1>;
[all …]
Dfsl-ls1088a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1088A family SoC.
5 * Copyright 2017-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
26 #address-cells = <1>;
[all …]
Dfsl-ls208xa.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
6 * Copyright 2017-2020 NXP
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
32 #address-cells = <1>;
[all …]
Dfsl-ls1043a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/thermal/thermal.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
Ddml2_core_utils.c1 // SPDX-License-Identifier: MIT
9 *remainder = ((dividend / divisor) - (int)(dividend / divisor) > 0); in dml2_core_utils_div_rem()
221 if (!fail_only || support->ScaleRatioAndTapsSupport == 0) in dml2_core_utils_print_mode_support_info()
222 dml2_printf("DML: support: ScaleRatioAndTapsSupport = %d\n", support->ScaleRatioAndTapsSupport); in dml2_core_utils_print_mode_support_info()
223 if (!fail_only || support->SourceFormatPixelAndScanSupport == 0) in dml2_core_utils_print_mode_support_info()
224 …dml2_printf("DML: support: SourceFormatPixelAndScanSupport = %d\n", support->SourceFormatPixelAndS… in dml2_core_utils_print_mode_support_info()
225 if (!fail_only || support->ViewportSizeSupport == 0) in dml2_core_utils_print_mode_support_info()
226 dml2_printf("DML: support: ViewportSizeSupport = %d\n", support->ViewportSizeSupport); in dml2_core_utils_print_mode_support_info()
227 if (!fail_only || support->LinkRateDoesNotMatchDPVersion == 1) in dml2_core_utils_print_mode_support_info()
228 …dml2_printf("DML: support: LinkRateDoesNotMatchDPVersion = %d\n", support->LinkRateDoesNotMatchDPV… in dml2_core_utils_print_mode_support_info()
[all …]
Ddml2_core_dcn4.c1 // SPDX-License-Identifier: MIT
82 ip_caps->pipe_count = ip_params->max_num_dpp; in patch_ip_caps_with_explicit_ip_params()
83 ip_caps->otg_count = ip_params->max_num_otg; in patch_ip_caps_with_explicit_ip_params()
84 ip_caps->num_dsc = ip_params->num_dsc; in patch_ip_caps_with_explicit_ip_params()
85 ip_caps->max_num_dp2p0_streams = ip_params->max_num_dp2p0_streams; in patch_ip_caps_with_explicit_ip_params()
86 ip_caps->max_num_dp2p0_outputs = ip_params->max_num_dp2p0_outputs; in patch_ip_caps_with_explicit_ip_params()
87 ip_caps->max_num_hdmi_frl_outputs = ip_params->max_num_hdmi_frl_outputs; in patch_ip_caps_with_explicit_ip_params()
88 ip_caps->rob_buffer_size_kbytes = ip_params->rob_buffer_size_kbytes; in patch_ip_caps_with_explicit_ip_params()
89 ip_caps->config_return_buffer_size_in_kbytes = ip_params->config_return_buffer_size_in_kbytes; in patch_ip_caps_with_explicit_ip_params()
90 …ip_caps->config_return_buffer_segment_size_in_kbytes = ip_params->config_return_buffer_segment_siz… in patch_ip_caps_with_explicit_ip_params()
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
Ddcn10_hwseq.c67 hws->ctx
69 hws->regs->reg
73 hws->shifts->field_name, hws->masks->field_name
88 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in print_microsec()
106 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn10_lock_all_pipes()
107 old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; in dcn10_lock_all_pipes()
108 pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn10_lock_all_pipes()
109 tg = pipe_ctx->stream_res.tg; in dcn10_lock_all_pipes()
115 if (pipe_ctx->top_pipe || in dcn10_lock_all_pipes()
116 !pipe_ctx->stream || in dcn10_lock_all_pipes()
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/display/dc/inc/hw/
Dtransform.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
157 struct rect viewport; member
204 uint32_t num);
/linux-6.14.4/arch/arm64/boot/dts/toshiba/
Dtmpv7708.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * (C) Copyright 2018 - 2020, Toshiba Corporation.
10 #include <dt-bindings/clock/toshiba,tmpv770x.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 /memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
23 #size-cells = <0>;
[all …]

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