non\-prefetch (full) in projects: linux-6.14.4

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/linux-6.14.4/tools/perf/pmu-events/arch/x86/amdzen5/
D	l2-cache.json	5 …"BriefDescription": "L2 cache requests of non-cacheable type (non-cached data and instructions rea… 11 …"BriefDescription": "L2 cache requests: from hardware prefetchers to prefetch directly into L2 (hi… 17 "BriefDescription": "L2 cache requests: prefetch directly into L2.", 41 …BriefDescription": "L2 cache requests: data cache reads including hardware and software prefetch.", 65 "BriefDescription": "L2 cache requests: non-coherent, non-cacheable LS sized reads.", 71 "BriefDescription": "L2 cache requests: coherent, non-cacheable LS sized reads.", 83 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: instructio… 89 …tion": "Core to L2 cache requests (not including L2 prefetch) with status: instruction cache hit n… 95 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: instructio… 101 …"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for instruction cache h… [all …]
D	load-store.json	5 …"BriefDescription": "Store-to-load conflicts (load unable to complete due to a non-forwardable con… 27 "BriefDescription": "Number of memory load operations dispatched to the load-store unit.", 33 "BriefDescription": "Number of memory store operations dispatched to the load-store unit.", 39 "BriefDescription": "Number of memory load-store operations dispatched to the load-store unit.", 45 "BriefDescription": "Number of memory operations dispatched to the load-store unit.", 61 "BriefDescription": "Store-to-load-forward (STLF) hits." 66 …"BriefDescription": "Non-cacheable store commits cancelled due to the non-cacheable commit buffer … 72 …iption": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for load-store all… 78 …"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for har… 84 …"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for all… [all …]
/linux-6.14.4/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/
D	other.json	3 "PublicDescription": "This event counts the occurrence count of the micro-operation split.", 6 "BriefDescription": "This event counts the occurrence count of the micro-operation split." 9 …o operation was committed because the oldest and uncommitted load/store/prefetch operation waits f… 12 …o operation was committed because the oldest and uncommitted load/store/prefetch operation waits f… 21 …instruction was committed because the oldest and uncommitted load/store/prefetch operation waits f… 24 …instruction was committed because the oldest and uncommitted load/store/prefetch operation waits f… 33 …instruction was committed because the oldest and uncommitted load/store/prefetch operation waits f… 36 …instruction was committed because the oldest and uncommitted load/store/prefetch operation waits f… 45 …unts every cycle that no instruction was committed due to the lack of an available prefetch port.", 48 …ounts every cycle that no instruction was committed due to the lack of an available prefetch port." [all …]
/linux-6.14.4/tools/perf/pmu-events/arch/x86/amdzen2/
D	memory.json	5 …"BriefDescription": "Non-forwardable conflict; used to reduce STLI's via software. All reasons. St… 6 …-to-load conflicts: A load was unable to complete due to a non-forwardable conflict with an older … 24 "BriefDescription": "Retired lock instructions. Non-speculative lock succeeded.", 84 "BriefDescription": "A non-cacheable store and the non-cacheable commit buffer is full." 90 …esses, although these are generally rare. Each increment represents an eight-byte access, although… 197 "BriefDescription": "Total Page Table Walks on I-side.", 215 "BriefDescription": "Total Page Table Walks on D-side.", 238 "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative).", 244 …"BriefDescription": "Software Prefetch Instructions Dispatched (Speculative). PrefetchNTA instruct… 250 …"BriefDescription": "Software Prefetch Instructions Dispatched (Speculative). See docAPM3 PREFETCH… [all …]
D	cache.json	5 …ion": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including hardware and soft… 11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.", 17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.", 23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.", 29 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request… 35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.", 41 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches a… 64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.", 70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab… 76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.", [all …]
/linux-6.14.4/tools/perf/pmu-events/arch/x86/amdzen3/
D	memory.json	5 …"BriefDescription": "Non-forwardable conflict; used to reduce STLI's via software. All reasons. St… 6 …-to-load conflicts: A load was unable to complete due to a non-forwardable conflict with an older … 24 "BriefDescription": "Retired lock instructions. Non-speculative lock succeeded.", 36 … "BriefDescription": "The number of retired CLFLUSH instructions. This is a non-speculative event." 46 …"BriefDescription": "Load-op-Store Dispatch. Dispatch of a single op that performs a load from and… 84 "BriefDescription": "A non-cacheable store and the non-cacheable commit buffer is full.", 91 …esses, although these are generally rare. Each increment represents an eight-byte access, although… 258 "BriefDescription": "Total Page Table Walks on I-side.", 276 "BriefDescription": "Total Page Table Walks on D-side.", 306 "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative).", [all …]
D	cache.json	5 …ion": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including hardware and soft… 11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.", 17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.", 23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.", 29 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request… 35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.", 41 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches a… 64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.", 70 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab… 76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.", [all …]
/linux-6.14.4/tools/perf/pmu-events/arch/x86/amdzen1/
D	cache.json	5 …etch windows transferred from IC pipe to DE instruction decoder (includes non-cacheable and cachea… 35 … instruction stream was being modified by another processor in an MP system - typically a highly u… 52 …l. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.", 58 …be (external or LS). The number of instruction cache lines invalidated. A non-SMC event is CMC (cr… 64 …iting fill response. The number of instruction cache lines invalidated. A non-SMC event is CMC (cr… 75 …ion": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including hardware and soft… 81 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.", 87 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.", 93 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.", 99 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request… [all …]
/linux-6.14.4/Documentation/devicetree/bindings/cache/
D	l2c2x0.yaml	`1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Rob Herring <[email protected]> 16 models (Note 1). Some of the properties that are just prefixed "cache-*" are 22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These 28 - $ref: /schemas/cache-controller.yaml# 33 - enum: 34 - arm,pl310-cache 35 - arm,l220-cache [all …]`
/linux-6.14.4/tools/perf/pmu-events/arch/x86/amdzen4/
D	cache.json	5 …iption": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for load-store all… 11 …"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for har… 17 …"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for all… 147 "EventName": "ls_pref_instr_disp.prefetch", 149 …"BriefDescription": "Software prefetch instructions dispatched (speculative) of type PrefetchT0 (m… 155 …"BriefDescription": "Software prefetch instructions dispatched (speculative) of type PrefetchW (mo… 161 …ption": "Software prefetch instructions dispatched (speculative) of type PrefetchNTA (move data wi… 167 "BriefDescription": "Software prefetch instructions dispatched (speculative) of all types.", 173 …prefetches that did not fetch data outside of the processor core as the PREFETCH instruction saw a… 179 …prefetches that did not fetch data outside of the processor core as the PREFETCH instruction saw a… [all …]
/linux-6.14.4/tools/perf/pmu-events/arch/powerpc/power8/
D	other.json	11 …"BriefDescription": "Cycles in 2-lpar mode. Threads 0-3 belong to Lpar0 and threads 4-7 belong to … 17 …cles in 4 LPAR mode. Threads 0-1 belong to lpar0, threads 2-3 belong to lpar1, threads 4-5 belong … 23 …p pump (prediction=correct) for all data types (demand load,data prefetch,inst prefetch,inst fetch… 24 …ip pump (prediction=correct) for all data types ( demand load,data,inst prefetch,inst fetch,xlate … 29 …s this scope was group pump for all data types (demand load,data prefetch,inst prefetch,inst fetch… 30 …his scope was group pump for all data types excluding data prefetch (demand load,inst prefetch,ins… 35 …ler than Initial Pump Scope for all data types (demand load,data prefetch,inst prefetch,inst fetch… 41 …n Initial Pump Scope (Chip) for all data types (demand load,data prefetch,inst prefetch,inst fetch… 42 …nitial pump was chip pumpfor all data types excluding data prefetch (demand load,inst prefetch,ins… 47 …s across all types of pumps for all data types (demand load,data prefetch,inst prefetch,inst fetch… [all …]
/linux-6.14.4/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/
D	sve.json	4 …ding the Advanced SIMD scalar instructions and the instructions listed in Non-SIMD SVE instruction… 8 …ecturally executed SVE instructions, including the instructions listed in Non-SIMD SVE instruction… 12 …ecturally executed SVE instructions, including the instructions listed in Non-SIMD SVE instruction… 20 "BriefDescription": "This event counts all architecturally executed micro-operations." 28 …ations due to scalar, Advanced SIMD, and SVE instructions listed in Floating-point instructions se… 32 …on": "This event counts architecturally executed floating-point fused multiply-add and multiply-su… 36 …"BriefDescription": "This event counts architecturally executed floating-point reciprocal estimate… 40 …uted floating-point convert operations due to the scalar, Advanced SIMD, and SVE floating-point co… 60 …"BriefDescription": "This event counts architecturally executed SVE 64-bit integer divide operatio… 76 …"BriefDescription": "This event counts architecturally executed SVE integer 64-bit x 64-bit multip… [all …]
D	l2_cache.json	12 …escription": "This event counts every write-back of data from the L2 cache caused by L2 replace, n… 40 …"BriefDescription": "This event counts every write-back of data from the L2 cache caused by L2 rep… 60 … "BriefDescription": "This event counts L2D_CACHE caused by hardware adjacent prefetch access." 95 …"BriefDescription": "This event counts every write-back of data from the L2 cache caused by L2 rep… 100 …BriefDescription": "This event counts every write-back of data from the L2 cache caused by non-tem… 105 …"BriefDescription": "This event counts every write-back of data from the L2 cache caused by DC ZVA… 110 "BriefDescription": "This event counts every flush-back (drop) of data from the L2 cache." 122 …efDescription": "This event counts access counted by L2D_CACHE that is due to a hardware prefetch." 126 …"BriefDescription": "This event counts hardware prefetch counted by L2D_CACHE_HWPRF that causes a … 150 …t counts fetch counted by either Level 2 data hardware prefetch or Level 2 data software prefetch." [all …]
/linux-6.14.4/tools/perf/pmu-events/arch/x86/goldmontplus/
D	cache.json	20 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.", 33 …prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely ind… 127 … Typically a load will receive this indication when some other load or prefetch missed the L1 cac… 176 "BriefDescription": "Memory uops retired that split a cache-line (Precise event capable)", 187 "BriefDescription": "Load uops retired that split a cache-line (Precise event capable)", 198 "BriefDescription": "Stores uops retired that split a cache-line (Precise event capable)", 217 …"BriefDescription": "Counts data reads (demand & prefetch) have any transaction responses from the… 223 …"PublicDescription": "Counts data reads (demand & prefetch) have any transaction responses from th… 228 "BriefDescription": "Counts data reads (demand & prefetch) hit the L2 cache.", 234 …"PublicDescription": "Counts data reads (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE… [all …]
/linux-6.14.4/tools/perf/pmu-events/arch/x86/snowridgex/
D	cache.json	20 …"BriefDescription": "Counts the number of demand and prefetch transactions that the External Queue… 24 …prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition wh… 81 …talled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", 85 …che or translation lookaside buffer (TLB) miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", 90 …the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM).", 94 …nstruction cache or translation lookaside buffer (TLB) miss which hit in DRAM or MMIO (non-DRAM).", 117 … the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", 125 …ber of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", 331 … were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was fo… 401 … were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was fo… [all …]
/linux-6.14.4/tools/perf/pmu-events/arch/x86/elkhartlake/
D	cache.json	20 …"BriefDescription": "Counts the number of demand and prefetch transactions that the External Queue… 24 …prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition wh… 81 …talled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", 85 …che or translation lookaside buffer (TLB) miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", 90 …the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM).", 94 …nstruction cache or translation lookaside buffer (TLB) miss which hit in DRAM or MMIO (non-DRAM).", 117 … the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", 125 …ber of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", 331 … were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was fo… 401 … were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was fo… [all …]
/linux-6.14.4/tools/perf/pmu-events/arch/x86/grandridge/
D	uncore-interconnect.json	20 …er of times D2C wasn't honoured even though the incoming request had d2c set for non cisgress txn", 47 "BriefDescription": "Counts reads to 1lm non persistent memory regions", 57 "BriefDescription": "All Writes - All Channels", 66 "BriefDescription": "Full Non-ISOCH - All Channels", 75 "BriefDescription": "Partial Non-ISOCH - All Channels", 84 "BriefDescription": "DDR - All Channels", 94 "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0", 104 "BriefDescription": "Prefetch CAM Inserts : XPT -All Channels", 109 "PublicDescription": "Prefetch CAM Inserts : XPT - All Channels", 114 "BriefDescription": "Prefetch CAM Occupancy : Channel 0", [all …]
D	uncore-cache.json	21 …"BriefDescription": "Distress signal assertion for dynamic prefetch throttle (DPT). Threshold for… 31 …"BriefDescription": "Distress signal assertion for dynamic prefetch throttle (DPT). Threshold for… 40 …"BriefDescription": "Distress signal assertion for dynamic prefetch throttle (DPT). Threshold for… 49 …"BriefDescription": "Counts when a normal (Non-Isochronous) full line write is issued from the CHA… 69 …"BriefDescription": "CHA to iMC Full Line Writes Issued : Partial Non-ISOCH : Counts the total num… 106 … LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numer… 172 … LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numer… 194 … LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numer… 210 "BriefDescription": "Cache Lookups: LLC Prefetch Requests to Locally Homed Memory", 216 … LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numer… [all …]
/linux-6.14.4/tools/perf/pmu-events/arch/x86/goldmont/
D	cache.json	20 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.", 33 …prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely ind… 127 … Typically a load will receive this indication when some other load or prefetch missed the L1 cac… 176 "BriefDescription": "Memory uops retired that split a cache-line (Precise event capable)", 187 "BriefDescription": "Load uops retired that split a cache-line (Precise event capable)", 198 "BriefDescription": "Stores uops retired that split a cache-line (Precise event capable)", 217 "BriefDescription": "Counts data reads (demand & prefetch) that hit the L2 cache.", 223 …"PublicDescription": "Counts data reads (demand & prefetch) that hit the L2 cache. Requires MSR_OF… 228 "BriefDescription": "Counts data reads (demand & prefetch) that miss the L2 cache.", 234 …"PublicDescription": "Counts data reads (demand & prefetch) that miss the L2 cache. Requires MSR_O… [all …]
/linux-6.14.4/tools/perf/pmu-events/arch/x86/jaketown/
D	cache.json	113 …ion": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from th… 178 "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch.", 186 "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch.", 386 "BriefDescription": "Core-originated cacheable demand requests missed LLC.", 394 "BriefDescription": "Core-originated cacheable demand requests that refer to LLC.", 402 …iption": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core c… 406 …-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (sa… 415 …his event counts retired load uops that hit in the last-level cache (L3) and were found in a non-m… 420 …n": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core … 483 …"PublicDescription": "This event counts retired load uops that hit in the last-level (L3) cache wi… [all …]
/linux-6.14.4/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/
D	mmu.json	9 …lk handled by the MMU. This event is not counted when it is accessible from Non-secure EL0 or EL1", 12 …alk handled by the MMU. This event is not counted when it is accessible from Non-secure EL0 or EL1" 15 …lk handled by the MMU. This event is not counted when it is accessible from Non-secure EL0 or EL1", 18 …alk handled by the MMU. This event is not counted when it is accessible from Non-secure EL0 or EL1" 33 …on": "Duration of a translation table walk requested by a Preload instruction or Prefetch request", 36 …ion": "Duration of a translation table walk requested by a Preload instruction or Prefetch request"
/linux-6.14.4/tools/perf/pmu-events/arch/arm64/
D	common-and-microarch.json	129 "PublicDescription": "Attributable Level 1 data cache write-back", 132 "BriefDescription": "Attributable Level 1 data cache write-back" 147 "PublicDescription": "Attributable Level 2 data cache write-back", 150 "BriefDescription": "Attributable Level 2 data cache write-back" 273 "PublicDescription": "Access to another socket in a multi-socket system", 276 "BriefDescription": "Access to another socket in a multi-socket system" 303 … "PublicDescription": "Attributable memory read access to another socket in a multi-socket system", 306 … "BriefDescription": "Attributable memory read access to another socket in a multi-socket system" 309 …"PublicDescription": "Level 1 data cache long-latency read miss. The counter counts each memory r… 312 "BriefDescription": "Level 1 data cache long-latency read miss" [all …]
/linux-6.14.4/tools/perf/pmu-events/arch/powerpc/power9/
D	marked.json	35 …as reloaded from local core's L2 with dispatch conflict due to an instruction fetch (not prefetch)" 80 …ache was reloaded from local core's L2 without conflict due to an instruction fetch (not prefetch)" 120 …other chip's memory on the same Node or Group (Distant) due to an instruction fetch (not prefetch)" 155 …r's Instruction cache was reloaded from local core's L2 due to an instruction fetch (not prefetch)" 195 …dified (M) data from another core's L3 on the same chip due to an instruction fetch (not prefetch)" 235 "BriefDescription": "Counts all Icache prefetch reloads ( includes demand turned into prefetch)" 265 …mp Scope was system pump for all data types excluding data prefetch (demand load,inst prefetch,ins… 270 …ish stall while waiting for the non-speculative finish of either a stcx waiting for its result or … 280 …nother chip's L4 on a different Node or Group (Distant) due to an instruction fetch (not prefetch)" 285 … pipeline cycles, or because the VSU is busy with multi-cycle instructions, or because of a write-… [all …]
D	other.json	60 …ferenced a line in an active fuzzy prefetch stream. The stream could have been allocated through t… 65 "BriefDescription": "Read-write data cache collisions" 90 "BriefDescription": "D-cache invalidates sent over the reload bus to the core" 95 …ruction cache was reloaded from the local chip's Memory due to an instruction fetch (not prefetch)" 115 …"BriefDescription": "Prefetch scope predictor selected GS or NNS, but was wrong because scope was … 200 "BriefDescription": "Read-write data cache collisions" 210 …riefDescription": "Prefetch stream allocated in the conservative phase by either the hardware pref… 275 "BriefDescription": "Prefetch stream allocated by the hardware prefetch mechanism" 280 …-word boundary, which causes it to require an additional slice than than what normally would be re… 300 "BriefDescription": "I-cache Invalidates sent over the realod bus to the core" [all …]
/linux-6.14.4/tools/perf/pmu-events/arch/x86/sandybridge/
D	cache.json	113 …ion": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from th… 178 "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch.", 186 "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch.", 386 "BriefDescription": "Core-originated cacheable demand requests missed LLC.", 394 "BriefDescription": "Core-originated cacheable demand requests that refer to LLC.", 402 …d load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. (Precise E… 407 …-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (sa… 412 …Retired load uops which data sources were HitM responses from shared LLC. (Precise Event - PEBS).", 417 …-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (sa… 422 …d uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. (Precise … [all …]

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