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/linux-6.14.4/Documentation/devicetree/bindings/interconnect/
Dmediatek,cci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interconnect/mediatek,cci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Cache Coherent Interconnect (CCI) frequency and voltage scaling
10 - Jia-Wei Chang <jia-[email protected]>
11 - Johnson Wang <[email protected]>
14 MediaTek Cache Coherent Interconnect (CCI) is a hardware engine used by
15 MT8183 and MT8186 SoCs to scale the frequency and adjust the voltage in
21 - mediatek,mt8183-cci
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/linux-6.14.4/arch/arm64/boot/dts/mediatek/
Dmt8183.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt8183-clk.h>
9 #include <dt-bindings/gce/mt8183-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8183-larb-port.h>
13 #include <dt-bindings/power/mt8183-power.h>
14 #include <dt-bindings/reset/mt8183-resets.h>
15 #include <dt-bindings/phy/phy.h>
16 #include <dt-bindings/thermal/thermal.h>
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Dmt8186.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 * Author: Allen-KH Cheng <allen-[email protected]>
6 /dts-v1/;
7 #include <dt-bindings/clock/mt8186-clk.h>
8 #include <dt-bindings/gce/mt8186-gce.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/memory/mt8186-memory-port.h>
12 #include <dt-bindings/pinctrl/mt8186-pinfunc.h>
13 #include <dt-bindings/power/mt8186-power.h>
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Dmt8183-evb.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
9 #include "mt8183.dtsi"
13 model = "MediaTek MT8183 evaluation board";
14 chassis-type = "embedded";
15 compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
27 stdout-path = "serial0:921600n8";
30 reserved-memory {
31 #address-cells = <2>;
32 #size-cells = <2>;
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Dmt6795.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mediatek,mt6795-clk.h>
12 #include <dt-bindings/gce/mediatek,mt6795-gce.h>
13 #include <dt-bindings/memory/mt6795-larb-port.h>
14 #include <dt-bindings/pinctrl/mt6795-pinfunc.h>
15 #include <dt-bindings/power/mt6795-power.h>
16 #include <dt-bindings/reset/mediatek,mt6795-resets.h>
20 interrupt-parent = <&sysirq>;
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Dmt8183-kukui.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include "mt8183.dtsi"
21 stdout-path = "serial0:115200n8";
25 compatible = "pwm-backlight";
27 power-supply = <&reg_vsys>;
28 enable-gpios = <&pio 176 0>;
29 brightness-levels = <0 1023>;
30 num-interpolated-steps = <1023>;
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/linux-6.14.4/Documentation/devicetree/bindings/soc/mediatek/
Dmtk-svs.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/mediatek/mtk-svs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Roger Lu <[email protected]>
11 - Matthias Brugger <[email protected]>
12 - Kevin Hilman <[email protected]>
17 different power domains(CPU/GPU/CCI) according to
24 - mediatek,mt8183-svs
25 - mediatek,mt8186-svs
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/linux-6.14.4/drivers/devfreq/
Dmtk-cci-devfreq.c1 // SPDX-License-Identifier: GPL-2.0-only
41 const struct mtk_ccifreq_platform_data *soc_data = drv->soc_data; in mtk_ccifreq_set_voltage()
42 struct device *dev = drv->dev; in mtk_ccifreq_set_voltage()
44 int retry_max = drv->vtrack_max; in mtk_ccifreq_set_voltage()
46 if (!drv->sram_reg) { in mtk_ccifreq_set_voltage()
47 ret = regulator_set_voltage(drv->proc_reg, new_voltage, in mtk_ccifreq_set_voltage()
48 drv->soc_data->proc_max_volt); in mtk_ccifreq_set_voltage()
52 pre_voltage = regulator_get_voltage(drv->proc_reg); in mtk_ccifreq_set_voltage()
58 pre_vsram = regulator_get_voltage(drv->sram_reg); in mtk_ccifreq_set_voltage()
64 new_vsram = clamp(new_voltage + soc_data->min_volt_shift, in mtk_ccifreq_set_voltage()
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/linux-6.14.4/drivers/cpufreq/
Dmediatek-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Pi-Cheng Chen <pi-[email protected]>
33 * 100mV < Vsram - Vproc < 200mV
71 if (cpumask_test_cpu(cpu, &info->cpus)) in mtk_cpu_dvfs_info_lookup()
81 const struct mtk_cpufreq_platform_data *soc_data = info->soc_data; in mtk_cpufreq_voltage_tracking()
82 struct regulator *proc_reg = info->proc_reg; in mtk_cpufreq_voltage_tracking()
83 struct regulator *sram_reg = info->sram_reg; in mtk_cpufreq_voltage_tracking()
85 int retry = info->vtrack_max; in mtk_cpufreq_voltage_tracking()
89 dev_err(info->cpu_dev, in mtk_cpufreq_voltage_tracking()
96 dev_err(info->cpu_dev, "invalid Vsram value: %d\n", pre_vsram); in mtk_cpufreq_voltage_tracking()
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/linux-6.14.4/drivers/soc/mediatek/
Dmtk-svs.c1 // SPDX-License-Identifier: GPL-2.0-only
22 #include <linux/nvmem-consumer.h>
147 inode->i_private); \
162 inode->i_private); \
177 * enum svsb_sw_id - SVS Bank Software ID
193 * enum svsb_type - SVS Bank 2-line: Type and Role
194 * @SVSB_TYPE_NONE: One-line type Bank - Global role
195 * @SVSB_TYPE_LOW: Two-line type Bank - Low bank role
196 * @SVSB_TYPE_HIGH: Two-line type Bank - High bank role
207 * enum svsb_phase - svs bank phase enumeration
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/linux-6.14.4/
DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-[email protected]
88 F: drivers/scsi/3w-*
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