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/linux-6.14.4/Documentation/devicetree/bindings/pci/
Dpci-msi.txt2 relationship between PCI devices and MSI controllers.
18 Requester ID. A mechanism is required to associate a device with both the MSI
22 For generic MSI bindings, see
23 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
30 -------------------
32 - msi-map: Maps a Requester ID to an MSI controller and associated
33 msi-specifier data. The property is an arbitrary number of tuples of
34 (rid-base,msi-controller,msi-base,length), where:
36 * rid-base is a single cell describing the first RID matched by the entry.
38 * msi-controller is a single phandle to an MSI controller
[all …]
/linux-6.14.4/drivers/pci/controller/
Dpcie-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
20 #include <linux/msi.h>
26 #include <linux/pci-ecam.h>
37 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
143 /* Offsets from INTR2_CPU and MSI_INTR2 BASE offsets */
165 #define BRCM_INT_PCI_MSI_MASK GENMASK(BRCM_INT_PCI_MSI_NR - 1, 0)
167 32 - BRCM_INT_PCI_MSI_LEGACY_NR)
169 /* MSI target addresses */
194 #define IDX_ADDR(pcie) ((pcie)->reg_offsets[EXT_CFG_INDEX])
[all …]
Dpcie-xilinx-nwl.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Based on pcie-xilinx.c, pci-tegra.c
6 * (C) Copyright 2014 - 2015, Xilinx, Inc.
16 #include <linux/msi.h>
21 #include <linux/pci-ecam.h>
34 /* Egress - Bridge translation registers */
44 /* Ingress - address translations */
52 /* Rxed msg fifo - Interrupt status registers */
111 /* MSI interrupt status mask bits */
147 struct nwl_msi { /* MSI information */
[all …]
Dpci-tegra.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (c) 2008-2009, NVIDIA Corporation.
11 * Bits taken from arch/arm/mach-dove/pcie.c
29 #include <linux/msi.h>
256 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
344 struct tegra_msi msi; member
356 static inline struct tegra_pcie *msi_to_pcie(struct tegra_msi *msi) in msi_to_pcie() argument
358 return container_of(msi, struct tegra_pcie, msi); in msi_to_pcie()
366 void __iomem *base; member
378 writel(value, pcie->afi + offset); in afi_writel()
[all …]
Dpcie-iproc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
9 #include <linux/pci-ecam.h>
10 #include <linux/msi.h>
17 #include <linux/irqchip/arm-gic-v3.h>
24 #include "pcie-iproc.h"
91 * struct iproc_pcie_ob_map - iProc PCIe outbound mapping controller-specific
138 * enum iproc_pcie_ib_map_type - iProc PCIe inbound mapping type
150 * struct iproc_pcie_ib_map - iProc PCIe inbound mapping controller-specific
159 * @imap_addr_offset: register offset between the upper and lower 32-bit
[all …]
Dpcie-rcar-host.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Renesas R-Car SoCs
4 * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
7 * arch/sh/drivers/pci/pcie-sh7786.c
8 * arch/sh/drivers/pci/ops-sh7786.c
9 * Copyright (C) 2009 - 2011 Paul Mundt
16 #include <linux/clk-provider.h>
24 #include <linux/msi.h>
34 #include "pcie-rcar.h"
50 struct rcar_msi msi; member
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/interrupt-controller/
Dloongson,pch-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson PCH MSI Controller
10 - Jiaxun Yang <[email protected]>
14 transforming interrupts from PCIe MSI into HyperTransport vectorized
19 const: loongson,pch-msi-1.0
24 loongson,msi-base-vec:
26 u32 value of the base of parent HyperTransport vector allocated
[all …]
Dal,alpine-msix.txt3 See arm,gic-v3.txt for SPI and MSI definitions.
7 - compatible: should be "al,alpine-msix"
8 - reg: physical base address and size of the registers
9 - interrupt-controller: identifies the node as an interrupt controller
10 - msi-controller: identifies the node as an PCI Message Signaled Interrupt
12 - al,msi-base-spi: SPI base of the MSI frame
13 - al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0
18 compatible = "al,alpine-msix";
20 interrupt-parent = <&gic>;
21 interrupt-controller;
[all …]
Darm,gic.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <[email protected]>
22 - $ref: /schemas/interrupt-controller.yaml#
27 - items:
28 - enum:
29 - arm,arm11mp-gic
30 - arm,cortex-a15-gic
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Dmarvell,odmi-controller.txt2 * Marvell ODMI for MSI support
4 Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller
5 which can be used by on-board peripheral for MSI interrupts.
9 - compatible : The value here should contain:
11 "marvell,ap806-odmi-controller", "marvell,odmi-controller".
13 - interrupt,controller : Identifies the node as an interrupt controller.
15 - msi-controller : Identifies the node as an MSI controller.
17 - marvell,odmi-frames : Number of ODMI frames available. Each frame
20 - reg : List of register definitions, one for each
23 - marvell,spi-base : List of GIC base SPI interrupts, one for each
[all …]
Dfsl,mu-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale/NXP i.MX Messaging Unit (MU) work as msi controller
10 - Frank Li <[email protected]>
23 registers (Processor A-side, Processor B-side).
25 MU can work as msi interrupt controller to do doorbell
28 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
33 - fsl,imx6sx-mu-msi
[all …]
Darm,gic-v3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <[email protected]>
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
26 - qcom,msm8996-gic-v3
[all …]
Dmsi-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/msi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MSI controller
10 - Marc Zyngier <[email protected]>
13 An MSI controller signals interrupts to a CPU when a write is made
14 to an MMIO address by some master. An MSI controller may feature a
18 "#msi-cells":
20 The number of cells in an msi-specifier, required if not zero.
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/misc/
Dfsl,qoriq-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/misc/fsl,qoriq-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <[email protected]>
13 The Freescale Management Complex (fsl-mc) is a hardware resource
15 network-oriented packet processing applications. After the fsl-mc
22 For an overview of the DPAA2 architecture and fsl-mc bus see:
26 same hardware "isolation context" and a 10-bit value called an ICID
31 between ICIDs and IOMMUs, so an iommu-map property is used to define
[all …]
/linux-6.14.4/drivers/pci/msi/
Dmsi.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
15 #include "msi.h"
21 * pci_msi_supported - check whether MSI may be enabled on a device
22 * @dev: pointer to the pci_dev data structure of MSI device function
26 * to determine if MSI/-X are supported for the device. If MSI/-X is
33 /* MSI must be globally enabled and supported by the device */ in pci_msi_supported()
37 if (!dev || dev->no_msi) in pci_msi_supported()
49 * Any bridge which does NOT route MSI transactions from its in pci_msi_supported()
[all …]
/linux-6.14.4/drivers/irqchip/
Dirq-gic-v2m.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * ARM GIC v2m MSI(-X) support
21 #include <linux/msi.h>
26 #include <linux/irqchip/arm-gic.h>
27 #include <linux/irqchip/arm-gic-common.h>
29 #include "irq-msi-lib.h"
34 * [25:16] lowest SPI assigned to MSI
36 * [9:0] Numer of SPIs assigned to MSI
52 /* APM X-Gene with GICv2m MSI_IIDR register value */
69 void __iomem *base; /* GICv2m virt address */ member
[all …]
Dirq-mvebu-icu.c5 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
18 #include <linux/msi.h>
23 #include "irq-msi-lib.h"
25 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
55 void __iomem *base; member
71 struct msi_domain_info *info = d->host_data; in mvebu_icu_translate()
72 struct mvebu_icu_msi_data *msi_data = info->chip_data; in mvebu_icu_translate()
73 struct mvebu_icu *icu = msi_data->icu; in mvebu_icu_translate()
76 if (WARN_ON(fwspec->param_count != param_count)) { in mvebu_icu_translate()
77 dev_err(icu->dev, "wrong ICU parameter count %d\n", in mvebu_icu_translate()
[all …]
Dirq-riscv-aplic-msi.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/irqchip/riscv-aplic.h>
13 #include <linux/irqchip/riscv-imsic.h>
15 #include <linux/msi.h>
21 #include "irq-riscv-aplic-main.h"
43 * The section "4.9.2 Special consideration for level-sensitive interrupt in aplic_msi_irq_retrigger_level()
44 * sources" of the RISC-V AIA specification says: in aplic_msi_irq_retrigger_level()
52 writel(d->hwirq, priv->regs + APLIC_SETIPNUM_LE); in aplic_msi_irq_retrigger_level()
60 * EOI handling is required only for level-triggered interrupts in aplic_msi_irq_eoi()
61 * when APLIC is in MSI mode. in aplic_msi_irq_eoi()
[all …]
Dirq-armada-370-xp.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
31 #include <linux/msi.h>
45 * +---------------+ +---------------+
47 * | per-CPU | | per-CPU |
51 * +---------------+ +---------------+
56 * +-------------------+
61 * +-------------------+
69 * registers, which are relative to "mpic->base".
[all …]
/linux-6.14.4/arch/arm64/boot/dts/marvell/
Darmada-ap80x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <2>;
25 compatible = "arm,psci-0.2";
29 reserved-memory {
30 #address-cells = <2>;
31 #size-cells = <2>;
[all …]
/linux-6.14.4/arch/arm64/boot/dts/broadcom/northstar2/
Dns2.dtsi35 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 #include <dt-bindings/clock/bcm-ns2.h>
40 interrupt-parent = <&gic>;
41 #address-cells = <2>;
42 #size-cells = <2>;
45 #address-cells = <2>;
46 #size-cells = <0>;
50 compatible = "arm,cortex-a57";
52 enable-method = "psci";
53 next-level-cache = <&CLUSTER0_L2>;
[all …]
/linux-6.14.4/include/linux/
Dpci-epc.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 #include <linux/pci-epf.h>
17 UNKNOWN_INTERFACE = -1,
36 * struct pci_epc_map - information about EPC memory for mapping a RC PCI
44 * @phys_base: base physical address of the allocated EPC memory for mapping the
47 * @virt_base: base virtual address of the allocated EPC memory for mapping the
65 * struct pci_epc_ops - set of function pointers for performing EPC operations
74 * @set_msi: ops to set the requested number of MSI interrupts in the MSI
76 * @get_msi: ops to get the number of MSI interrupts allocated by the RC from
77 * the MSI capability register
[all …]
/linux-6.14.4/arch/sparc/kernel/
Dpci_fire.c1 // SPDX-License-Identifier: GPL-2.0
2 /* pci_fire.c: Sun4u platform PCI-E controller support.
10 #include <linux/msi.h>
33 struct iommu *iommu = pbm->iommu; in pci_fire_pbm_iommu_init()
38 /* No virtual-dma property on these guys, use largest size. */ in pci_fire_pbm_iommu_init()
39 vdma[0] = 0xc0000000; /* base */ in pci_fire_pbm_iommu_init()
45 iommu->iommu_control = pbm->pbm_regs + FIRE_IOMMU_CONTROL; in pci_fire_pbm_iommu_init()
46 iommu->iommu_tsbbase = pbm->pbm_regs + FIRE_IOMMU_TSBBASE; in pci_fire_pbm_iommu_init()
47 iommu->iommu_flush = pbm->pbm_regs + FIRE_IOMMU_FLUSH; in pci_fire_pbm_iommu_init()
48 iommu->iommu_flushinv = pbm->pbm_regs + FIRE_IOMMU_FLUSHINV; in pci_fire_pbm_iommu_init()
[all …]
/linux-6.14.4/drivers/spi/
Dspi-pci1xxxx.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/dma-mapping.h>
14 #include <linux/msi.h>
21 #define DRV_NAME "spi-pci1xxxx"
105 /* x refers to SPI Host Controller HW instance id in the below macros - 0 or 1 */
197 writel(SPI_SYSLOCK, par->reg_base + SPI_SYSLOCK_REG); in pci1xxxx_set_sys_lock()
198 return readl(par->reg_base + SPI_SYSLOCK_REG); in pci1xxxx_set_sys_lock()
212 writel(0x0, par->reg_base + SPI_SYSLOCK_REG); in pci1xxxx_release_sys_lock()
217 struct pci_dev *pdev = spi_bus->dev; in pci1xxxx_check_spi_can_dma()
228 dev_err(&pdev->dev, "Error failed to acquire syslock\n"); in pci1xxxx_check_spi_can_dma()
[all …]
/linux-6.14.4/drivers/pci/controller/mobiveil/
Dpcie-mobiveil.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 #include <linux/msi.h>
103 /* supported number of MSI interrupts */
106 /* MSI registers */
136 struct mobiveil_msi { /* MSI information */
152 void __iomem *config_axi_slave_base; /* endpoint config base */
158 struct mobiveil_msi msi; member
168 void __iomem *csr_axi_slave_base; /* root port config base */
169 void __iomem *apb_csr_base; /* MSI register base */
170 phys_addr_t pcie_reg_base; /* Physical PCIe Controller Base */

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