Home
last modified time | relevance | path

Searched +full:mpfs +full:- +full:spi (Results 1 – 11 of 11) sorted by relevance

/linux-6.14.4/Documentation/devicetree/bindings/spi/
Dmicrochip,mpfs-spi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip FPGA {Q,}SPI Controllers
10 SPI and QSPI controllers on Microchip PolarFire SoC and the "soft"/
14 - Conor Dooley <[email protected]>
19 - items:
20 - enum:
21 - microchip,mpfs-qspi
[all …]
/linux-6.14.4/arch/riscv/boot/dts/microchip/
Dmpfs.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
11 compatible = "microchip,mpfs";
14 #address-cells = <1>;
15 #size-cells = <0>;
16 timebase-frequency = <1000000>;
[all …]
Dmpfs-icicle-kit.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
6 #include "mpfs.dtsi"
7 #include "mpfs-icicle-kit-fabric.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/leds/common.h>
12 model = "Microchip PolarFire-SoC Icicle Kit";
13 compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
14 "microchip,mpfs";
[all …]
Dmpfs-tysom-m.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Original all-in-one devicetree:
4 * Copyright (C) 2020-2022 - Aldec
6 * Copyright (C) 2022 - Conor Dooley <[email protected]>
9 /dts-v1/;
11 #include "mpfs.dtsi"
12 #include "mpfs-tysom-m-fabric.dtsi"
15 model = "Aldec TySOM-M-MPFS250T-REV2";
16 compatible = "aldec,tysom-m-mpfs250t-rev2", "microchip,mpfs";
31 stdout-path = "serial1:115200n8";
[all …]
Dmpfs-beaglev-fire.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
7 #include "mpfs.dtsi"
8 #include "mpfs-beaglev-fire-fabric.dtsi"
14 #address-cells = <2>;
15 #size-cells = <2>;
16 model = "BeagleBoard BeagleV-Fire";
17 compatible = "beagle,beaglev-fire", "microchip,mpfs";
[all …]
/linux-6.14.4/drivers/soc/microchip/
Dmpfs-sys-controller.c1 // SPDX-License-Identifier: GPL-2.0
3 * Microchip PolarFire SoC (MPFS) system controller driver
5 * Copyright (c) 2020-2021 Microchip Corporation. All rights reserved.
16 #include <linux/spi/spi.h>
21 #include <soc/microchip/mpfs.h>
48 reinit_completion(&sys_controller->c); in mpfs_blocking_transaction()
50 ret = mbox_send_message(sys_controller->chan, msg); in mpfs_blocking_transaction()
52 dev_warn(sys_controller->client.dev, "MPFS sys controller service timeout\n"); in mpfs_blocking_transaction()
67 if (!wait_for_completion_timeout(&sys_controller->c, timeout)) { in mpfs_blocking_transaction()
68 ret = -EBADMSG; in mpfs_blocking_transaction()
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/soc/microchip/
Dmicrochip,mpfs-sys-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-sys-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) system controller
10 - Conor Dooley <[email protected]>
17 https://onlinedocs.microchip.com/pr/GUID-1409CF11-8EF9-4C24-A94E-70979A688632-en-US-1/index.html
27 const: microchip,mpfs-sys-controller
29 microchip,bitstream-flash:
32 The SPI flash connected to the system controller's QSPI controller.
[all …]
/linux-6.14.4/drivers/firmware/microchip/
Dmpfs-auto-update.c1 // SPDX-License-Identifier: GPL-2.0
8 * Copyright (c) 2022-2023 Microchip Corporation. All rights reserved.
21 #include <soc/microchip/mpfs.h>
43 * SPI Flash layout example:
44 * |------------------------------| 0x0000000
46 * | SPI "directories" |
47 * |------------------------------| 0x0000400
51 * |------------------------------| 0x0100400
54 * |------------------------------| 0x1500400
57 * |------------------------------| 0x2900400
[all …]
/linux-6.14.4/drivers/spi/
Dspi-microchip-core.c1 // SPDX-License-Identifier: (GPL-2.0)
3 * Microchip CoreSPI SPI controller driver
5 * Copyright (c) 2018-2022 Microchip Technology Inc. and its subsidiaries
21 #include <linux/spi/spi.h>
107 u32 clk_gen; /* divider for spi output clock generated by the controller */
116 static inline u32 mchp_corespi_read(struct mchp_corespi *spi, unsigned int reg) in mchp_corespi_read() argument
118 return readl(spi->regs + reg); in mchp_corespi_read()
121 static inline void mchp_corespi_write(struct mchp_corespi *spi, unsigned int reg, u32 val) in mchp_corespi_write() argument
123 writel(val, spi->regs + reg); in mchp_corespi_write()
126 static inline void mchp_corespi_disable(struct mchp_corespi *spi) in mchp_corespi_disable() argument
[all …]
/linux-6.14.4/drivers/rtc/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
44 This clock should be battery-backed, so that it reads the correct
45 time when the system boots from a power-off state. Otherwise, your
141 once-per-second update interrupts, used for synchronization.
159 will be called rtc-test.
173 will be called rtc-88pm860x.
183 will be called rtc-88pm80x.
193 will be called rtc-88pm886.
197 tristate "Abracon AB-RTCMC-32.768kHz-B5ZE-S3"
200 AB-RTCMC-32.768kHz-B5ZE-S3 I2C RTC chip.
[all …]
/linux-6.14.4/
DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-[email protected]
88 F: drivers/scsi/3w-*
[all …]