Searched +full:mpc8610 +full:- +full:dma +full:- +full:channel (Results 1 – 7 of 7) sorted by relevance
| /linux-6.14.4/Documentation/devicetree/bindings/sound/ |
| D | fsl,ssi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <[email protected]>
13 Notes on fsl,playback-dma and fsl,capture-dma
14 On SOCs that have an SSI, specific DMA channels are hard-wired for playback
15 and capture. On the MPC8610, for example, SSI1 must use DMA channel 0 for
16 playback and DMA channel 1 for capture. SSI2 must use DMA channel 2 for
17 playback and DMA channel 3 for capture. The developer can choose which
18 DMA controller to use, but the channels themselves are hard-wired. The
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| /linux-6.14.4/sound/soc/fsl/ |
| D | fsl_dma.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * mpc8610-pcm.h - ALSA PCM interface for the Freescale MPC8610 SoC
31 } channel[4]; member
74 /* ECLNDAR takes bits 32-36 of the CLNDAR register */
96 * List Descriptor for extended chaining mode DMA operations.
98 * The CLSDAR register points to the first (in a linked-list) List
99 * Descriptor. Each object must be aligned on a 32-byte boundary. Each
100 * list descriptor points to a linked-list of link Descriptors.
111 * Link Descriptor for basic and extended chaining mode DMA operations.
113 * A Link Descriptor points to a single DMA buffer. Each link descriptor
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| D | fsl_dma.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // Freescale DMA ALSA SoC PCM driver
7 // Copyright 2007-2010 Freescale Semiconductor, Inc.
9 // This driver implements ASoC support for the Elo DMA controller, which is
10 // the DMA controller on Freescale 83xx, 85xx, and 86xx SOCs. In ALSA terms,
11 // the PCM driver is what handles the DMA buffer.
16 #include <linux/dma-mapping.h>
39 * The formats that the DMA controller supports, which is anything
61 struct ccsr_dma_channel __iomem *channel; member
67 * The number of DMA links to use. Two is the bare minimum, but if you
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| D | fsl_ssi.c | 1 // SPDX-License-Identifier: GPL-2.0
7 // Copyright 2007-2010 Freescale Semiconductor, Inc.
9 // Some notes why imx-pcm-fiq is used instead of DMA on some boards:
16 // we receive in our (PCM-) data stream. The only chance we have is to
43 #include <linux/dma/imx-dma.h>
53 #include "imx-pcm.h"
55 /* Define RX and TX to index ssi->regvals array; Can be 0 or 1 only */
66 * (bit-endianness must match byte-endianness). Processors typically write
68 * written in. So if the host CPU is big-endian, then only big-endian
91 * - SSI inputs external bit clock and outputs frame sync clock -- CBM_CFS
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| /linux-6.14.4/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | dma.txt | 1 * Freescale DMA Controllers
3 ** Freescale Elo DMA Controller
4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
9 - compatible : must include "fsl,elo-dma"
10 - reg : DMA General Status Register, i.e. DGSR which contains
11 status for all the 4 DMA channels
12 - ranges : describes the mapping between the address space of the
13 DMA channels and the address space of the DMA controller
14 - cell-index : controller index. 0 for controller @ 0x8100
15 - interrupts : interrupt specifier for DMA IRQ
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| /linux-6.14.4/arch/powerpc/boot/dts/fsl/ |
| D | p1022si-post.dtsi | 36 #address-cells = <2>;
37 #size-cells = <1>;
39 * The localbus on the P1022 is not a simple-bus because of the eLBC
42 compatible = "fsl,p1022-elbc", "fsl,elbc";
49 compatible = "fsl,mpc8548-pcie";
51 #size-cells = <2>;
52 #address-cells = <3>;
53 bus-range = <0 255>;
54 clock-frequency = <33333333>;
59 #interrupt-cells = <1>;
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| /linux-6.14.4/drivers/spi/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
44 If your system has an master-capable SPI controller (which
56 by providing a high-level interface to send memory-like commands.
66 This enables support for SPI-NAND mode on the Airoha NAND
68 is implemented as a SPI-MEM controller.
107 to a single device like spi-nor (nvram), input device controller
166 supports spi-mem interface.
245 this code to manage the per-word or per-transfer accesses to the
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