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/linux-6.14.4/Documentation/devicetree/bindings/power/
Dmti,mips-cpc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/mti,mips-cpc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MIPS Cluster Power Controller
10 Defines a location of the MIPS Cluster Power Controller registers.
13 - Paul Burton <[email protected]>
17 const: mti,mips-cpc
22 used to map the MIPS CPC registers block.
26 - compatible
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/linux-6.14.4/arch/mips/include/asm/
Dmips-cpc.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Author: Paul Burton <paul.burton@mips.com>
8 # error Please include asm/mips-cps.h rather than asm/mips-cpc.h
17 /* The base address of the CPC registers */
21 * mips_cpc_default_phys_base - retrieve the default physical base address of
22 * the CPC
26 * implemented per-platform.
31 * mips_cpc_probe - probe for a Cluster Power Controller
34 * a CPC is successfully detected, else -errno.
41 return -ENODEV; in mips_cpc_probe()
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Dpm-cps.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Author: Paul Burton <paul.burton@mips.com>
11 * The CM & CPC can only handle coherence & power control on a per-core basis,
13 * enter or exit states requiring CM or CPC assistance in unison.
25 CPS_PM_NC_WAIT, /* MIPS wait instruction, non-coherent */
32 * cps_pm_support_state - determine whether the system supports a PM state
40 * cps_pm_enter_state - enter a PM state
43 * Enter the given PM state. If coupled_coherence is non-zero then it is
45 * each coupled CPU. Returns 0 on successful entry & exit, otherwise -errno.
Dmips-cps.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Author: Paul Burton <paul.burton@mips.com>
106 #include <asm/mips-cm.h>
107 #include <asm/mips-cpc.h>
108 #include <asm/mips-gic.h>
111 * mips_cps_numclusters - return the number of clusters present in the system
124 * mips_cps_cluster_config - return (GCR|CPC)_CONFIG from a cluster
146 * GCR_CONFIG via the redirect region, since the CPC is always in mips_cps_cluster_config()
158 * mips_cps_numcores - return the number of cores present in a cluster
175 * mips_cps_numiocu - return the number of IOCUs present in a cluster
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Ddsemul.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Author: Paul Burton <paul.burton@mips.com>
24 * mips_dsemul() - 'Emulate' an instruction from a branch delay slot
30 * Emulate or execute an arbitrary MIPS instruction within the context of
41 * do_dsemulret() - Return from a delay slot 'emulation' frame
47 * passed as the cpc parameter to mips_dsemul().
61 * dsemul_thread_cleanup() - Cleanup thread 'emulation' frame
78 * dsemul_thread_rollback() - Rollback from an 'emulation' frame
99 * dsemul_mm_cleanup() - Cleanup per-mm delay slot 'emulation' state
103 * for delay slot 'emulation' book-keeping is freed. This is to be called
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Dmips-cm.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Author: Paul Burton <paul.burton@mips.com>
8 # error Please include asm/mips-cps.h rather than asm/mips-cm.h
21 /* The base address of the CM L2-only sync region */
25 * mips_cm_phys_base - retrieve the physical base address of the CM
36 * mips_cm_l2sync_phys_base - retrieve the physical base address of the CM
37 * L2-sync region
40 * L2-cache only region. It provides a default implementation which reads the
49 * mips_cm_is64 - determine CM register width
54 * or vice-versa. This variable indicates the width of the memory accesses
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/linux-6.14.4/arch/mips/kernel/
Dmips-cpc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Author: Paul Burton <paul.burton@mips.com>
14 #include <asm/mips-cps.h>
28 cpc_node = of_find_compatible_node(of_root, NULL, "mti,mips-cpc"); in mips_cpc_default_phys_base()
40 * mips_cpc_phys_base - retrieve the physical base address of the CPC
56 /* If the CPC is already enabled, leave it so */ in mips_cpc_phys_base()
66 /* Enable the CPC, mapped at the default address */ in mips_cpc_phys_base()
81 return -ENODEV; in mips_cpc_probe()
85 return -ENXIO; in mips_cpc_probe()
95 /* Systems with CM >= 3 lock the CPC via mips_cm_lock_other */ in mips_cpc_lock_other()
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Dpm-cps.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Author: Paul Burton <paul.burton@mips.com>
13 #include <asm/asm-offsets.h>
17 #include <asm/mips-cps.h>
20 #include <asm/pm-cps.h>
22 #include <asm/smp-cps.h>
26 * cps_nc_entry_fn - type of a generated non-coherent state entry function
28 * @nc_ready_count: pointer to a non-coherent mapping of the core ready_count
30 * The code entering & exiting non-coherent states is generated at runtime
33 * core-specific code particularly for cache routines. If coupled_coherence
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for the Linux/MIPS kernel.
6 extra-y := vmlinux.lds
8 obj-y += head.o branch.o cmpxchg.o elf.o entry.o genex.o idle.o irq.o \
14 obj-y += cpu-r3k-probe.o
16 obj-y += cpu-probe.o
26 obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm1480.o
27 obj-$(CONFIG_CEVT_R4K) += cevt-r4k.o
28 obj-$(CONFIG_CEVT_DS1287) += cevt-ds1287.o
29 obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o
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Dmips-r2-to-r6-emul.c10 * MIPS R2 user space instruction emulator for MIPS R6
28 #include <asm/mips-r2-to-r6-emul.h>
65 pr_info("MIPS R2-to-R6 Emulator Enabled!"); in mipsr2emu_enable()
72 * mipsr6_emul - Emulate some frequent R2/R5/R6 instructions in delay slot
83 regs->regs[MIPSInst_RT(ir)] = in mipsr6_emul()
84 (s32)regs->regs[MIPSInst_RS(ir)] + in mipsr6_emul()
92 regs->regs[MIPSInst_RT(ir)] = in mipsr6_emul()
93 (s64)regs->regs[MIPSInst_RS(ir)] + in mipsr6_emul()
101 return -SIGFPE; in mipsr6_emul()
106 regs->regs[MIPSInst_RD(ir)] = in mipsr6_emul()
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Dsmp-cps.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Author: Paul Burton <paul.burton@mips.com>
19 #include <asm/mips-cps.h>
22 #include <asm/pm-cps.h>
26 #include <asm/smp-cps.h>
115 0x0, CSEGX_SIZE - 1); in allocate_cps_vecs()
128 end = SZ_4G - 1; in allocate_cps_vecs()
142 return -ENOMEM; in allocate_cps_vecs()
193 for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) { in cps_smp_setup()
233 /* If we have an FPU, enroll ourselves in the FPU-full mask */ in cps_smp_setup()
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Dmips-cm.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Author: Paul Burton <paul.burton@mips.com>
11 #include <asm/mips-cps.h>
20 "0x04", "cpc", "0x06", "0x07"
198 return (cmgcr & MIPS_CMGCRF_BASE) << (36 - 32); in mips_cm_phys_base()
206 * If the L2-only sync region is already enabled then leave it at it's in mips_cm_l2sync_phys_base()
222 /* L2-only sync was introduced with CM major revision 6 */ in mips_cm_probe_l2sync()
256 return -ENODEV; in mips_cm_probe()
260 return -ENXIO; in mips_cm_probe()
269 return -ENODEV; in mips_cm_probe()
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Dcps-vec.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Author: Paul Burton <paul.burton@mips.com>
10 #include <asm/asm-offsets.h>
17 #include <asm/smp-cps.h>
51 * Set dest to non-zero if the core supports the MT ASE, else zero. If
66 * Set dest to non-zero if the core supports MIPSr6 multithreading
131 /* Skip core-level init if we started up coherent */
135 /* Perform any further required core-level initialisation */
236 /* Set exclusive TC, non-active, master */
242 /* Set TC non-active, non-allocatable */
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/linux-6.14.4/arch/mips/boot/dts/img/
Dboston.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/clock/boston-clock.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/mips-gic.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
15 stdout-path = "uart0:115200";
23 #address-cells = <1>;
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Dpistachio.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/pistachio-clk.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/mips-gic.h>
11 #include <dt-bindings/reset/pistachio-resets.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
19 interrupt-parent = <&gic>;
22 #address-cells = <1>;
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/linux-6.14.4/arch/mips/include/asm/mips-boards/
Dmalta.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Carsten Langgaard, carstenl@mips.com
4 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
6 * Defines of the Malta board specific address-MAP, registers, etc.
13 #include <asm/mips-boards/msc01_pci.h>
16 /* Mips interrupt controller found in SOCit variations */
55 * CPC Specific definitions
71 * Malta RTC-device indirect register access.
/linux-6.14.4/arch/mips/boot/dts/ralink/
Dmt7621.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 #include <dt-bindings/interrupt-controller/mips-gic.h>
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/clock/mt7621-clk.h>
5 #include <dt-bindings/reset/mt7621-reset.h>
8 compatible = "mediatek,mt7621-soc";
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
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/linux-6.14.4/drivers/clocksource/
Dmips-gic-timer.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
4 #define pr_fmt(fmt) "mips-gic-timer: " fmt
17 #include <asm/mips-cps.h>
55 int cpu = cpumask_first(evt->cpumask); in gic_next_event()
67 res = ((int)(gic_read_count() - cnt) >= 0) ? -ETIME : 0; in gic_next_event()
76 cd->event_handler(cd); in gic_compare_interrupt()
90 cd->name = "MIPS GIC"; in gic_clockevent_cpu_init()
91 cd->features = CLOCK_EVT_FEAT_ONESHOT | in gic_clockevent_cpu_init()
94 cd->rating = 350; in gic_clockevent_cpu_init()
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/linux-6.14.4/arch/mips/ralink/
Dmt7621.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include <asm/smp-ops.h>
19 #include <asm/mips-cps.h>
20 #include <asm/mach-ralink/ralink_regs.h>
21 #include <asm/mach-ralink/mt7621.h>
35 entry = resource_list_first_type(&bridge->windows, IORESOURCE_MEM); in pcibios_root_bridge_prepare()
38 return -EINVAL; in pcibios_root_bridge_prepare()
46 mask = ~(entry->res->end - entry->res->start) & CM_GCR_REGn_MASK_ADDRMASK; in pcibios_root_bridge_prepare()
47 WARN_ON(mask && BIT(ffz(~mask)) - 1 != ~mask); in pcibios_root_bridge_prepare()
49 write_gcr_reg1_base(entry->res->start); in pcibios_root_bridge_prepare()
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/linux-6.14.4/arch/mips/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
2 config MIPS config
145 bool "Generic board-agnostic MIPS kernel"
287 Build a generic DT-based kernel image that boots on select
288 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
379 This enables support for DEC's MIPS based workstations. For details
380 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
381 DECstation porting pages on <http://decstation.unix-ag.org/>.
417 This a family of machines based on the MIPS R4030 chipset which was
419 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
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/linux-6.14.4/
DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-[email protected]
88 F: drivers/scsi/3w-*
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/linux-6.14.4/drivers/block/
Dfloppy.c1 // SPDX-License-Identifier: GPL-2.0-only
11 * 02.12.91 - Changed to static variables to indicate need for reset
29 * call "floppy-on" directly, but have to set a special timer interrupt
34 * 28.02.92 - made track-buffering routines, based on the routines written
39 * Automatic floppy-detection and formatting written by Werner Almesberger
41 * the floppy-change signal detection.
45 * 1992/7/22 -- Hennus Bergman: Added better error reporting, fixed
49 * 1992/9/17: Added DMA allocation & DMA functions. -- hhb.
56 * modeled after the freeware MS-DOS program fdformat/88 V1.8 by
65 * 1993/4/29 -- Linus -- cleaned up the timer handling in the kernel, and
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