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/linux-6.14.4/Documentation/devicetree/bindings/net/
Dfsl,cpm-mdio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,cpm-mdio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale CPM MDIO Device
10 - Frank Li <[email protected]>
15 - enum:
16 - fsl,pq1-fec-mdio
17 - fsl,cpm2-mdio-bitbang
18 - items:
[all …]
Dmdio-mux-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Properties for an MDIO bus multiplexer/switch controlled by GPIO pins.
10 - Andrew Lunn <[email protected]>
13 This is a special case of a MDIO bus multiplexer. One or more GPIO
17 - $ref: /schemas/net/mdio-mux.yaml#
21 const: mdio-mux-gpio
30 - compatible
[all …]
Dmediatek,star-emac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek,star-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bartosz Golaszewski <[email protected]>
14 It's compliant with 802.3 standards and supports half- and full-duplex
15 modes with flow-control as well as CRC offloading and VLAN tags.
18 - $ref: ethernet-controller.yaml#
23 - mediatek,mt8516-eth
24 - mediatek,mt8518-eth
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/pinctrl/
Dlantiq,pinctrl-xway.txt4 - compatible: "lantiq,<chip>-pinctrl", where <chip> is:
10 - reg: Should contain the physical address and length of the gpio/pinmux
13 Please refer to pinctrl-bindings.txt in this directory for details of the
15 phrase "pin configuration node".
17 Lantiq's pin configuration nodes act as a container for an arbitrary number of
19 pin, a group, or a list of pins or groups. This configuration can include the
20 mux function to select on those group(s), and two pin configuration parameters:
21 pull-up and open-drain
27 other words, a subnode that lists a mux function but no pin configuration
28 parameters implies no information about any pin configuration parameters.
[all …]
Dralink,rt2880-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/ralink,rt2880-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ralink RT2880 Pin Controller
10 - Arınç ÜNAL <[email protected]>
11 - Sergio Paracuellos <[email protected]>
14 Ralink RT2880 pin controller for RT2880 SoC.
15 The pin controller can only set the muxing of pin groups. Muxing individual
20 const: ralink,rt2880-pinctrl
[all …]
Dralink,rt305x-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/ralink,rt305x-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ralink RT305X Pin Controller
10 - Arınç ÜNAL <[email protected]>
11 - Sergio Paracuellos <[email protected]>
14 Ralink RT305X pin controller for RT3050, RT3052, and RT3350 SoCs.
15 The pin controller can only set the muxing of pin groups. Muxing individual
20 const: ralink,rt305x-pinctrl
[all …]
Dmediatek,mt7620-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7620-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek MT7620 Pin Controller
10 - Arınç ÜNAL <[email protected]>
11 - Sergio Paracuellos <[email protected]>
14 MediaTek MT7620 pin controller for MT7620 SoC.
15 The pin controller can only set the muxing of pin groups. Muxing individual
20 const: ralink,mt7620-pinctrl
[all …]
Dralink,rt3352-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/ralink,rt3352-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ralink RT3352 Pin Controller
10 - Arınç ÜNAL <[email protected]>
11 - Sergio Paracuellos <[email protected]>
14 Ralink RT3352 pin controller for RT3352 SoC.
15 The pin controller can only set the muxing of pin groups. Muxing individual
20 const: ralink,rt3352-pinctrl
[all …]
Dralink,rt3883-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/ralink,rt3883-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ralink RT3883 Pin Controller
10 - Arınç ÜNAL <[email protected]>
11 - Sergio Paracuellos <[email protected]>
14 Ralink RT3883 pin controller for RT3883 SoC.
15 The pin controller can only set the muxing of pin groups. Muxing individual
20 const: ralink,rt3883-pinctrl
[all …]
Dmediatek,mt7621-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7621-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek MT7621 Pin Controller
10 - Arınç ÜNAL <[email protected]>
11 - Sergio Paracuellos <[email protected]>
14 MediaTek MT7621 pin controller for MT7621 SoC.
15 The pin controller can only set the muxing of pin groups. Muxing individual
20 const: ralink,mt7621-pinctrl
[all …]
Dlantiq,pinctrl-falcon.txt4 - compatible: "lantiq,pinctrl-falcon"
5 - reg: Should contain the physical address and length of the gpio/pinmux
8 Please refer to pinctrl-bindings.txt in this directory for details of the
10 phrase "pin configuration node".
12 Lantiq's pin configuration nodes act as a container for an arbitrary number of
14 pin, a group, or a list of pins or groups. This configuration can include the
15 mux function to select on those group(s), and two pin configuration parameters:
16 pull-up and open-drain
22 other words, a subnode that lists a mux function but no pin configuration
23 parameters implies no information about any pin configuration parameters.
[all …]
Dairoha,en7581-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/airoha,en7581-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Airoha EN7581 Pin Controller
10 - Lorenzo Bianconi <[email protected]>
13 The Airoha's EN7581 Pin controller is used to control SoC pins.
17 const: airoha,en7581-pinctrl
22 gpio-controller: true
24 '#gpio-cells':
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/net/dsa/
Dqca8k.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - John Crispin <[email protected]>
13 If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
16 ID. To declare the internal mdio-bus configuration, declare an MDIO node in
18 PHY it is connected to. In this config, an internal mdio-bus is registered and
19 the MDIO master is used for communication. Mixed external and internal
20 mdio-bus configurations are not supported by the hardware.
27 - enum:
[all …]
Dmicrochip,ksz.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Vasut <[email protected]>
11 - Woojung Huh <[email protected]>
14 - $ref: /schemas/spi/spi-peripheral-props.yaml#
21 - microchip,ksz8765
22 - microchip,ksz8794
23 - microchip,ksz8795
24 - microchip,ksz8863
[all …]
/linux-6.14.4/drivers/pinctrl/renesas/
Dpinctrl-rzn1.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014-2018 Renesas Electronics Europe Limited
9 #include <dt-bindings/pinctrl/rzn1-pinctrl.h>
19 #include <linux/pinctrl/pinconf-generic.h>
26 #include "../pinctrl-utils.h"
45 * the multiplexing for Ethernet MDIO signals.
49 * going from 0 to 61. Level 3 allows selection of MDIO functions which can be
51 * level 2 functions that can select MDIO, and two MDIO channels so we have four
57 * 72 to 79 is 72 + MDIO0 source for level 2 MDIO function.
59 * 88 to 95 is 88 + MDIO1 source for level 2 MDIO function.
[all …]
/linux-6.14.4/drivers/net/phy/
Dicplus.c1 // SPDX-License-Identifier: GPL-2.0+
33 /* IP101A/G - IP1001 */
42 #define IP101A_G_IRQ_PIN_USED BIT(15) /* INTR pin used */
69 /* The 32-pin IP101GR package can re-configure the mode of the RXER/INTR_32 pin
70 * (pin number 21). The hardware default is RXER (receive error) mode. But it
102 err = mdiobus_write(phydev->mdio.bus, 30, 0, 0x175c); in ip175c_config_init()
107 err = mdiobus_read(phydev->mdio.bus, 30, 0); in ip175c_config_init()
113 err = mdiobus_write(phydev->mdio.bus, 29, 31, 0x175c); in ip175c_config_init()
118 err = mdiobus_write(phydev->mdio.bus, 29, 22, 0x420); in ip175c_config_init()
124 err = mdiobus_write(phydev->mdio.bus, i, in ip175c_config_init()
[all …]
/linux-6.14.4/arch/powerpc/boot/dts/
Dkmeter1.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * 2008-2011 DENX Software Engineering GmbH
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
28 #address-cells = <1>;
29 #size-cells = <0>;
34 d-cache-line-size = <32>; // 32 bytes
35 i-cache-line-size = <32>; // 32 bytes
36 d-cache-size = <32768>; // L1, 32K
[all …]
/linux-6.14.4/drivers/pinctrl/
Dpinctrl-xway.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/pinctrl/pinmux-xway.c
4 * based on linux/drivers/pinctrl/pinmux-pxa910.c
21 #include "pinctrl-lantiq.h"
31 /* we have 2 mux bits that can be set for each pin */
66 .pin = a, \
110 /* --------- ase related code --------- */
114 /* pin f0 f1 f2 f3 */
139 MFP_XWAY(GPIO24, GPIO, EBU, EBU2, MDIO),
142 MFP_XWAY(GPIO27, GPIO, EBU, NONE, MDIO),
[all …]
Dpinctrl-falcon.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/pinctrl/pinmux-falcon.c
4 * based on linux/drivers/pinctrl/pinmux-pxa910.c
22 #include "pinctrl-lantiq.h"
54 .pin = a, \
106 /* pin f0 f1 f2 f3 */
114 MFP_FALCON(GPIO7, MDIO, GPIO, NONE, NONE),
115 MFP_FALCON(GPIO8, MDIO, GPIO, NONE, NONE),
187 GRP_MUX("mdio", MDIO, pins_mdio),
202 static const char * const ltq_mdio_grps[] = {"mdio"};
[all …]
/linux-6.14.4/drivers/net/mdio/
Dmdio-gpio.c1 // SPDX-License-Identifier: GPL-2.0
3 * GPIO based MDIO bitbang driver.
7 * by Laurent Pinchart <laurentp@cse-semaphore.com>
22 #include <linux/mdio-bitbang.h>
23 #include <linux/mdio-gpio.h>
26 #include <linux/platform_data/mdio-gpio.h>
32 struct gpio_desc *mdc, *mdio, *mdo; member
38 bitbang->mdc = devm_gpiod_get_index(dev, NULL, MDIO_GPIO_MDC, in mdio_gpio_get_data()
40 if (IS_ERR(bitbang->mdc)) in mdio_gpio_get_data()
41 return PTR_ERR(bitbang->mdc); in mdio_gpio_get_data()
[all …]
/linux-6.14.4/drivers/net/ethernet/freescale/fs_enet/
Dmii-bitbang.c1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <linux/mdio-bitbang.h>
60 bb_set(bitbang->dir, bitbang->mdio_msk); in mdio_dir()
62 bb_clr(bitbang->dir, bitbang->mdio_msk); in mdio_dir()
65 in_be32(bitbang->dir); in mdio_dir()
71 return bb_read(bitbang->dat, bitbang->mdio_msk); in mdio_read()
74 static inline void mdio(struct mdiobb_ctrl *ctrl, int what) in mdio() function
79 bb_set(bitbang->dat, bitbang->mdio_msk); in mdio()
81 bb_clr(bitbang->dat, bitbang->mdio_msk); in mdio()
84 in_be32(bitbang->dat); in mdio()
[all …]
/linux-6.14.4/arch/powerpc/platforms/pasemi/
Dgpio_mdio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2006-2007 PA Semi, Inc
9 * Based on drivers/net/fs_enet/mii-bitbang.c.
34 #define MDC_PIN(bus) (((struct gpio_priv *)bus->priv)->mdc_pin)
35 #define MDIO_PIN(bus) (((struct gpio_priv *)bus->priv)->mdio_pin)
124 /* tri-state our MDIO I/O pin so we can read */ in gpio_mdio_read()
190 * Tri-state the MDIO line. in gpio_mdio_write()
202 /*nothing here - dunno how to reset it*/ in gpio_mdio_reset()
209 struct device *dev = &ofdev->dev; in gpio_mdio_probe()
210 struct device_node *np = ofdev->dev.of_node; in gpio_mdio_probe()
[all …]
/linux-6.14.4/arch/powerpc/platforms/82xx/
Dep8248e.c1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <linux/mdio-bitbang.h>
49 struct device_node *np = of_find_compatible_node(NULL, NULL, "fsl,pq2-pic"); in ep8248e_pic_init()
51 printk(KERN_ERR "PIC init: can not find cpm-pic node\n"); in ep8248e_pic_init()
116 node = of_get_parent(ofdev->dev.of_node); in ep8248e_mdio_probe()
119 return -ENODEV; in ep8248e_mdio_probe()
121 ret = of_address_to_resource(ofdev->dev.of_node, 0, &res); in ep8248e_mdio_probe()
127 return -ENOMEM; in ep8248e_mdio_probe()
129 bus->name = "ep8248e-mdio-bitbang"; in ep8248e_mdio_probe()
130 bus->parent = &ofdev->dev; in ep8248e_mdio_probe()
[all …]
/linux-6.14.4/arch/arm/boot/dts/broadcom/
Dbcm2711.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/soc/bcm2835-pm.h>
10 #address-cells = <2>;
11 #size-cells = <1>;
13 interrupt-parent = <&gicv2>;
16 compatible = "brcm,bcm2711-vc5";
20 clk_27MHz: clk-27M {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
[all …]
/linux-6.14.4/arch/powerpc/boot/dts/fsl/
Dmpc8569mds.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /include/ "mpc8569si-pre.dtsi"
13 #address-cells = <2>;
14 #size-cells = <2>;
15 interrupt-parent = <&mpic>;
40 #address-cells = <1>;
41 #size-cells = <1>;
42 compatible = "cfi-flash";
44 bank-width = <1>;
45 device-width = <1>;
[all …]

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