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/linux-6.14.4/arch/mips/boot/dts/img/
Dpistachio.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/pistachio-clk.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/mips-gic.h>
11 #include <dt-bindings/reset/pistachio-resets.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
19 interrupt-parent = <&gic>;
22 #address-cells = <1>;
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/net/
Dfsl,cpm-mdio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,cpm-mdio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <[email protected]>
15 - enum:
16 - fsl,pq1-fec-mdio
17 - fsl,cpm2-mdio-bitbang
18 - items:
19 - const: fsl,mpc8272ads-mdio-bitbang
[all …]
/linux-6.14.4/drivers/net/mdio/
Dmdio-gpio.c1 // SPDX-License-Identifier: GPL-2.0
7 * by Laurent Pinchart <laurentp@cse-semaphore.com>
22 #include <linux/mdio-bitbang.h>
23 #include <linux/mdio-gpio.h>
26 #include <linux/platform_data/mdio-gpio.h>
32 struct gpio_desc *mdc, *mdio, *mdo; member
38 bitbang->mdc = devm_gpiod_get_index(dev, NULL, MDIO_GPIO_MDC, in mdio_gpio_get_data()
40 if (IS_ERR(bitbang->mdc)) in mdio_gpio_get_data()
41 return PTR_ERR(bitbang->mdc); in mdio_gpio_get_data()
43 bitbang->mdio = devm_gpiod_get_index(dev, NULL, MDIO_GPIO_MDIO, in mdio_gpio_get_data()
[all …]
/linux-6.14.4/arch/powerpc/boot/dts/
Dkmeter1.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * 2008-2011 DENX Software Engineering GmbH
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
28 #address-cells = <1>;
29 #size-cells = <0>;
34 d-cache-line-size = <32>; // 32 bytes
35 i-cache-line-size = <32>; // 32 bytes
36 d-cache-size = <32768>; // L1, 32K
[all …]
Dmgcoge.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
9 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
28 d-cache-line-size = <32>;
29 i-cache-line-size = <32>;
30 d-cache-size = <16384>;
31 i-cache-size = <16384>;
[all …]
Dksi8560.dts15 /dts-v1/;
22 #address-cells = <1>;
23 #size-cells = <1>;
32 #address-cells = <1>;
33 #size-cells = <0>;
38 d-cache-line-size = <32>;
39 i-cache-line-size = <32>;
40 d-cache-size = <0x8000>; /* L1, 32K */
41 i-cache-size = <0x8000>; /* L1, 32K */
42 timebase-frequency = <0>; /* From U-boot */
[all …]
/linux-6.14.4/drivers/net/ethernet/freescale/fs_enet/
Dmii-bitbang.c1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <linux/mdio-bitbang.h>
60 bb_set(bitbang->dir, bitbang->mdio_msk); in mdio_dir()
62 bb_clr(bitbang->dir, bitbang->mdio_msk); in mdio_dir()
65 in_be32(bitbang->dir); in mdio_dir()
71 return bb_read(bitbang->dat, bitbang->mdio_msk); in mdio_read()
79 bb_set(bitbang->dat, bitbang->mdio_msk); in mdio()
81 bb_clr(bitbang->dat, bitbang->mdio_msk); in mdio()
84 in_be32(bitbang->dat); in mdio()
87 static inline void mdc(struct mdiobb_ctrl *ctrl, int what) in mdc() function
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/arm/marvell/
Dcp110-system-controller.txt6 giving access to numerous features: clocks, pin-muxing and many other
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the CP110 system controller
18 -------
23 - a set of core clocks
24 - a set of gateable clocks
28 - The first cell must be 0 or 1. 0 for the core clocks and 1 for the
30 - The second cell identifies the particular core clock or gateable
34 - Core clocks
35 - 0 0 APLL
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/pinctrl/
Dqcom,ipq5018-tlmm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,ipq5018-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm IPQ5018 TLMM pin controller
10 - Bjorn Andersson <[email protected]>
11 - Krzysztof Kozlowski <[email protected]>
14 Top Level Mode Multiplexer pin controller in Qualcomm IPQ5018 SoC.
18 const: qcom,ipq5018-tlmm
26 gpio-reserved-ranges:
[all …]
Dqcom,ipq8074-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,ipq8074-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm IPQ8074 TLMM pin controller
10 - Bjorn Andersson <[email protected]>
11 - Krzysztof Kozlowski <[email protected]>
14 Top Level Mode Multiplexer pin controller in Qualcomm IPQ8074 SoC.
18 const: qcom,ipq8074-pinctrl
26 gpio-reserved-ranges:
[all …]
Dqcom,ipq4019-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,ipq4019-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <[email protected]>
13 Top Level Mode Multiplexer pin controller in Qualcomm IPQ4019 SoC.
16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
20 const: qcom,ipq4019-pinctrl
28 gpio-reserved-ranges: true
31 "-state$":
[all …]
Dmediatek,mt7622-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7622-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek MT7622 Pin Controller
10 - Sean Wang <[email protected]>
13 The MediaTek's MT7622 Pin controller is used to control SoC pins.
18 - mediatek,mt7622-pinctrl
19 - mediatek,mt7629-pinctrl
24 reg-names:
[all …]
Dqcom,ipq9574-tlmm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,ipq9574-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <[email protected]>
11 - Krzysztof Kozlowski <[email protected]>
14 Top Level Mode Multiplexer pin controller in Qualcomm IPQ9574 SoC.
18 const: qcom,ipq9574-tlmm
26 gpio-reserved-ranges:
30 gpio-line-names:
[all …]
/linux-6.14.4/drivers/pinctrl/mvebu/
Dpinctrl-armada-cp110.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 #include "pinctrl-mvebu.h"
22 * Even if the pin controller is the same the MMP available depend on the SoC
24 * - In Armada7K (single CP) almost all the MPPs are available (except the
26 * - In Armada8K (dual CP) the MPPs are split into 2 parts, MPPs 0-31 from
27 * CPS, and MPPs 32-62 from CPM, the below flags (V_ARMADA_8K_CPM,
62 MPP_FUNCTION(10, "ge", "mdc")),
74 MPP_FUNCTION(10, "xg", "mdc")),
97 MPP_FUNCTION(10, "ge", "mdc")),
266 MPP_FUNCTION(8, "ge", "mdc"),
[all …]
/linux-6.14.4/arch/arm/boot/dts/gemini/
Dgemini-sq201.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
9 #include <dt-bindings/input/input.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
24 stdout-path = &uart0;
28 compatible = "gpio-keys";
30 button-setup {
31 debounce-interval = <100>;
32 wakeup-source;
[all …]
Dgemini-sl93512r.dts1 // SPDX-License-Identifier: GPL-2.0
5 * "Gemini324 EV-Board" before Storm acquired Storlink Semiconductor.
9 /dts-v1/;
12 #include <dt-bindings/input/input.h>
15 model = "Storlink Semiconductor Gemini324 EV-Board / Storm Semiconductor SL93512R_BRD";
17 #address-cells = <1>;
18 #size-cells = <1>;
28 stdout-path = &uart0;
32 compatible = "gpio-keys";
34 button-wps {
[all …]
Dgemini-dlink-dir-685.dts2 * Device Tree file for D-Link DIR-685 Xtreme N Storage Router
5 /dts-v1/;
8 #include <dt-bindings/input/input.h>
11 model = "D-Link DIR-685 Xtreme N Storage Router";
12 compatible = "dlink,dir-685", "cortina,gemini";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 /* 128 MB SDRAM in 2 x Hynix HY5DU121622DTP-D43 */
24 stdout-path = "uart0:19200n8";
28 compatible = "gpio-keys";
[all …]
/linux-6.14.4/arch/powerpc/platforms/82xx/
Dkm82xx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright 2008-2011 DENX Software Engineering GmbH
31 np = of_find_compatible_node(NULL, NULL, "fsl,pq2-pic"); in km82xx_pic_init()
34 pr_err("PIC init: can not find cpm-pic node\n"); in km82xx_pic_init()
42 int port, pin, flags; member
106 /* MDC */
137 const struct cpm_pin *pin = &km82xx_pins[i]; in init_ioports() local
138 cpm2_set_pin(pin->port, pin->pin, pin->flags); in init_ioports()
154 setbits32(&cpm2_immr->im_ioport.iop_pdata, 1 << (31 - 10)); in init_ioports()
156 clrbits32(&cpm2_immr->im_ioport.iop_pdata, 1 << (31 - 11)); in init_ioports()
[all …]
/linux-6.14.4/arch/arm/boot/dts/st/
Dstih407-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "st-pincfg.h"
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 /* 0-5: PIO_SBC */
18 /* 10-19: PIO_FRONT0 */
31 /* 30-35: PIO_REAR */
38 /* 40-42: PIO_FLASH */
45 pin-controller-sbc@961f080 {
46 #address-cells = <1>;
47 #size-cells = <1>;
[all …]
/linux-6.14.4/arch/powerpc/platforms/pasemi/
Dgpio_mdio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2006-2007 PA Semi, Inc
9 * Based on drivers/net/fs_enet/mii-bitbang.c.
34 #define MDC_PIN(bus) (((struct gpio_priv *)bus->priv)->mdc_pin)
35 #define MDIO_PIN(bus) (((struct gpio_priv *)bus->priv)->mdio_pin)
124 /* tri-state our MDIO I/O pin so we can read */ in gpio_mdio_read()
190 * Tri-state the MDIO line. in gpio_mdio_write()
202 /*nothing here - dunno how to reset it*/ in gpio_mdio_reset()
209 struct device *dev = &ofdev->dev; in gpio_mdio_probe()
210 struct device_node *np = ofdev->dev.of_node; in gpio_mdio_probe()
[all …]
/linux-6.14.4/arch/arm64/boot/dts/exynos/
Dexynosautov9-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's ExynosAutov9 SoC pin-mux and pin-config device tree source
7 * Samsung's ExynosAutov9 SoC pin-mux and pin-config options are listed as
11 #include "exynos-pinctrl.h"
14 gpa0: gpa0-gpio-bank {
15 gpio-controller;
16 #gpio-cells = <2>;
17 interrupt-controller;
18 #interrupt-cells = <2>;
19 interrupt-parent = <&gic>;
[all …]
/linux-6.14.4/drivers/pinctrl/bcm/
Dpinctrl-ns.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/pinctrl/pinconf-generic.h>
44 { 6, "mdc", (void *)(FLAG_BCM4709 | FLAG_BCM53012) },
172 return -EINVAL; in ns_pinctrl_set_mux()
174 for (i = 0; i < group->grp.npins; i++) in ns_pinctrl_set_mux()
175 unset |= BIT(group->grp.pins[i]); in ns_pinctrl_set_mux()
177 tmp = readl(ns_pinctrl->base); in ns_pinctrl_set_mux()
179 writel(tmp, ns_pinctrl->base); in ns_pinctrl_set_mux()
196 .name = "pinctrl-ns",
202 { .compatible = "brcm,bcm4708-pinmux", .data = (void *)FLAG_BCM4708, },
[all …]
/linux-6.14.4/drivers/pinctrl/qcom/
Dpinctrl-ipq5018.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2019-2021, 2023 The Linux Foundation. All rights reserved.
10 #include "pinctrl-msm.h"
102 #define DECLARE_MSM_GPIO_PINS(pin) \ argument
103 static const unsigned int gpio##pin##_pins[] = { pin }
638 MSM_PIN_FUNCTION(mdc),
717 PINGROUP(36, mdc, qdss_tracedata_b, _, wsi_clk3, _, _, _, _, _),
746 { .compatible = "qcom,ipq5018-tlmm", },
753 .name = "ipq5018-tlmm",
Dpinctrl-ipq4019.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include "pinctrl-msm.h"
115 #define DECLARE_QCA_GPIO_PINS(pin) \ argument
116 static const unsigned int gpio##pin##_pins[] = { pin }
502 QCA_PIN_FUNCTION(mdc),
532 PINGROUP(7, mdc, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
619 PINGROUP(52, qpic, mdc, pcie, i2s_tx, NA, NA, NA, tm, wifi0, wifi1, NA,
703 { .compatible = "qcom,ipq4019-pinctrl", },
709 .name = "ipq4019-pinctrl",
Dpinctrl-ipq9574.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
10 #include "pinctrl-msm.h"
120 #define DECLARE_MSM_GPIO_PINS(pin) \ argument
121 static const unsigned int gpio##pin##_pins[] = { pin }
656 MSM_PIN_FUNCTION(mdc),
740 PINGROUP(38, mdc, _, cri_trng0, _, _, _, _, _, _),
771 59, -1
791 { .compatible = "qcom,ipq9574-tlmm", },
798 .name = "ipq9574-tlmm",

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