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/linux-6.14.4/drivers/mmc/host/
Dsdhci-s3c.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* linux/drivers/mmc/host/sdhci-s3c.c
14 #include <linux/dma-mapping.h>
16 #include <linux/platform_data/mmc-sdhci-s3c.h>
35 #define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR BIT(31)
36 #define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK BIT(30)
37 #define S3C_SDHCI_CTRL2_CDINVRXD3 BIT(29)
38 #define S3C_SDHCI_CTRL2_SLCARDOUT BIT(28)
48 #define S3C_SDHCI_CTRL2_ENFBCLKTX BIT(15)
49 #define S3C_SDHCI_CTRL2_ENFBCLKRX BIT(14)
[all …]
/linux-6.14.4/drivers/net/wireless/intel/iwlwifi/fw/api/
Drs.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2022, 2024 Intel Corporation
12 * enum iwl_tlc_mng_cfg_flags - options for TLC config flags
27 IWL_TLC_MNG_CFG_FLAGS_STBC_MSK = BIT(0),
28 IWL_TLC_MNG_CFG_FLAGS_LDPC_MSK = BIT(1),
29 IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK = BIT(2),
30 IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_1_MSK = BIT(3),
31 IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_2_MSK = BIT(4),
32 IWL_TLC_MNG_CFG_FLAGS_EHT_EXTRA_LTF_MSK = BIT(6),
36 * enum iwl_tlc_mng_cfg_cw - channel width options
[all …]
Dlocation.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2015-2017 Intel Deutschland GmbH
4 * Copyright (C) 2018-2022 Intel Corporation
11 * enum iwl_location_subcmd_ids - location group command IDs
86 * struct iwl_tof_config_cmd - ToF configuration
88 * @one_sided_disabled: indicates if one-sided is disabled (or not)
100 * enum iwl_tof_bandwidth - values for iwl_tof_range_req_ap_entry.bandwidth
101 * @IWL_TOF_BW_20_LEGACY: 20 MHz non-HT
118 * enum iwl_tof_algo_type - Algorithym type for range measurement request
130 * enum iwl_tof_mcsi_ntfy - Enable/Disable MCSI notifications
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/clock/ti/
Dti,divider-clock.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/ti/ti,divider-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tero Kristo <[email protected]>
13 This clock It assumes a register-mapped adjustable clock rate divider
25 ti,index-starts-at-one - valid divisor values start at 1, not the default
32 ti,index-power-of-two - valid divisor values are powers of two. E.g:
49 Any zero value in this array means the corresponding bit-value is invalid
53 unless the divider array is provided, min and max dividers. Optionally
[all …]
/linux-6.14.4/sound/usb/
Dformat.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/usb/audio-v2.h>
10 #include <linux/usb/audio-v3.h>
38 switch (fp->protocol) { in parse_audio_format_i_type()
45 fp->iface, fp->altsetting, format); in parse_audio_format_i_type()
48 sample_width = fmt->bBitResolution; in parse_audio_format_i_type()
49 sample_bytes = fmt->bSubframeSize; in parse_audio_format_i_type()
56 sample_width = fmt->bBitResolution; in parse_audio_format_i_type()
57 sample_bytes = fmt->bSubslotSize; in parse_audio_format_i_type()
62 fp->dsd_raw = true; in parse_audio_format_i_type()
[all …]
/linux-6.14.4/drivers/clk/mvebu/
Ddove-divider.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
15 #include "dove-divider.h"
32 DIV_CTRL1_N_RESET_MASK = BIT(10),
56 val = readl_relaxed(dc->base + DIV_CTRL0); in dove_get_divider()
57 val >>= dc->div_bit_start; in dove_get_divider()
59 divider = val & ~(~0 << dc->div_bit_size); in dove_get_divider()
61 if (dc->divider_table) in dove_get_divider()
62 divider = dc->divider_table[divider]; in dove_get_divider()
67 static int dove_calc_divider(const struct dove_clk *dc, unsigned long rate, in dove_calc_divider() argument
[all …]
/linux-6.14.4/drivers/memory/tegra/
Dtegra20-emc.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/interconnect-provider.h>
95 #define EMC_CLKCHANGE_REQ_ENABLE BIT(0)
96 #define EMC_CLKCHANGE_PD_ENABLE BIT(1)
97 #define EMC_CLKCHANGE_SR_ENABLE BIT(2)
99 #define EMC_TIMING_UPDATE BIT(0)
101 #define EMC_REFRESH_OVERFLOW_INT BIT(3)
102 #define EMC_CLKCHANGE_COMPLETE_INT BIT(4)
103 #define EMC_MRR_DIVLD_INT BIT(5)
105 #define EMC_DBG_READ_MUX_ASSEMBLY BIT(0)
[all …]
Dtegra30-emc.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Based on downstream driver from NVIDIA and tegra124-emc.c
6 * Copyright (C) 2011-2014 NVIDIA Corporation
9 * Copyright (C) 2019 GRATE-DRIVER project
18 #include <linux/interconnect-provider.h>
151 #define EMC_STATUS_TIMING_UPDATE_STALLED BIT(23)
153 #define EMC_MODE_SET_DLL_RESET BIT(8)
154 #define EMC_MODE_SET_LONG_CNT BIT(26)
156 #define EMC_SELF_REF_CMD_ENABLED BIT(0)
159 #define DRAM_DEV_SEL_0 BIT(31)
[all …]
/linux-6.14.4/drivers/clk/
Dclk-versaclock3.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/clk-provider.h>
17 #define VC3_GENERAL_CTR_DIV1_SRC_SEL BIT(3)
18 #define VC3_GENERAL_CTR_PLL3_REFIN_SEL BIT(2)
21 #define VC3_PLL3_M_DIV1 BIT(7)
22 #define VC3_PLL3_M_DIV2 BIT(6)
29 #define VC3_PLL3_CHARGE_PUMP_CTRL_OUTDIV3_SRC_SEL BIT(7)
32 #define VC3_PLL1_CTRL_OUTDIV5_PLL1_MDIV_DOUBLER BIT(7)
35 #define VC3_PLL1_M_DIV1 BIT(7)
36 #define VC3_PLL1_M_DIV2 BIT(6)
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/display/modules/freesync/
Dfreesync.c2 * Copyright 2016-2023 Advanced Micro Devices, Inc.
34 /* Refresh rate ramp at a fixed rate of 65 Hz/second */
38 /* Threshold to exit/exit BTR (to avoid frequent enter-exits at the lower limit) */
42 /* Threshold to exit fixed refresh rate */
72 core_freesync->dc = dc; in mod_freesync_create()
73 return &core_freesync->public; in mod_freesync_create()
119 * 10000) * stream->timing.h_total, in calc_duration_in_us_from_v_total()
120 stream->timing.pix_clk_100hz)); in calc_duration_in_us_from_v_total()
127 unsigned int max_hw_v_total = stream->ctx->dc->caps.max_v_total; in calc_max_hardware_v_total()
129 if (stream->ctx->dc->caps.vtotal_limited_by_fp2) { in calc_max_hardware_v_total()
[all …]
/linux-6.14.4/drivers/clk/ti/
Ddivider.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Tero Kristo <t-[email protected]>
10 #include <linux/clk-provider.h>
26 for (clkt = table; clkt->div; clkt++) in _get_table_div()
27 if (clkt->val == val) in _get_table_div()
28 return clkt->div; in _get_table_div()
38 if (divider->table) { in _setup_mask()
41 for (clkt = divider->table; clkt->div; clkt++) in _setup_mask()
42 if (clkt->val > max_val) in _setup_mask()
43 max_val = clkt->val; in _setup_mask()
[all …]
/linux-6.14.4/drivers/clk/sunxi-ng/
Dccu_mp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 #include <linux/clk-provider.h>
13 static unsigned long ccu_mp_find_best(unsigned long parent, unsigned long rate, in ccu_mp_find_best() argument
25 if (tmp_rate > rate) in ccu_mp_find_best()
28 if ((rate - tmp_rate) < (rate - best_rate)) { in ccu_mp_find_best()
44 unsigned long rate, in ccu_mp_find_best_with_parent_adj() argument
58 * unsigned long in rate * m * p below in ccu_mp_find_best_with_parent_adj()
61 maxdiv = min(ULONG_MAX / rate, maxdiv); in ccu_mp_find_best_with_parent_adj()
70 if (rate * div == parent_rate_saved) { in ccu_mp_find_best_with_parent_adj()
[all …]
/linux-6.14.4/drivers/clk/imx/
Dclk-sscg-pll.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 * https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf#page=834
11 #include <linux/clk-provider.h>
33 #define PLL_LOCK_MASK BIT(31)
34 #define PLL_PD_MASK BIT(7)
65 #define SSCG_PLL_BYPASS1_MASK BIT(5)
66 #define SSCG_PLL_BYPASS2_MASK BIT(4)
102 val = readl_relaxed(pll->base + PLL_CFG0); in clk_sscg_pll_wait_lock()
106 return readl_poll_timeout(pll->base, val, val & PLL_LOCK_MASK, in clk_sscg_pll_wait_lock()
115 int new_diff = temp_setup->fout - temp_setup->fout_request; in clk_sscg_pll2_check_match()
[all …]
/linux-6.14.4/sound/soc/sof/
Dipc3-pcm.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
11 #include "ipc3-priv.h"
13 #include "sof-priv.h"
14 #include "sof-audio.h"
26 return -EINVAL; in sof_ipc3_pcm_hw_free()
28 if (!spcm->prepared[substream->stream]) in sof_ipc3_pcm_hw_free()
33 stream.comp_id = spcm->stream[substream->stream].comp_id; in sof_ipc3_pcm_hw_free()
36 return sof_ipc_tx_message_no_reply(sdev->ipc, &stream, sizeof(stream)); in sof_ipc3_pcm_hw_free()
46 struct sof_ipc_fw_version *v = &sdev->fw_ready.version; in sof_ipc3_pcm_hw_params()
47 struct snd_pcm_runtime *runtime = substream->runtime; in sof_ipc3_pcm_hw_params()
[all …]
/linux-6.14.4/sound/soc/fsl/
Dimx-card.c1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright 2017-2021 NXP
14 #include <sound/soc-dapm.h>
33 * @rmin: min rate
34 * @rmax: max rate
36 * @wmax: max frame ratio
50 unsigned int max; member
55 * struct imx_card_plat_data - specific info for codecs
59 * @support_rates: supported sample rate
60 * @support_tdm_rates: supported sample rate for tdm mode
[all …]
/linux-6.14.4/drivers/watchdog/
Drza_wdt.c1 // SPDX-License-Identifier: GPL-2.0
23 #define WTSCR_WT BIT(6)
24 #define WTSCR_TME BIT(5)
32 #define WRCSR_RSTE BIT(6)
52 unsigned long rate = clk_get_rate(priv->clk); in rza_wdt_calc_timeout() local
55 if (priv->cks == CKS_4BIT) { in rza_wdt_calc_timeout()
56 ticks = DIV_ROUND_UP(timeout * rate, DIVIDER_4BIT); in rza_wdt_calc_timeout()
63 priv->count = 256 - ticks; in rza_wdt_calc_timeout()
67 priv->count = 0; in rza_wdt_calc_timeout()
71 timeout, priv->count); in rza_wdt_calc_timeout()
[all …]
/linux-6.14.4/drivers/iio/dac/
Dad5755.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * AD5755, AD5755-1, AD5757, AD5735, AD5737 Digital to analog converters driver
50 #define AD5755_DAC_INT_EN BIT(8)
51 #define AD5755_DAC_CLR_EN BIT(7)
52 #define AD5755_DAC_OUT_EN BIT(6)
53 #define AD5755_DAC_INT_CURRENT_SENSE_RESISTOR BIT(5)
54 #define AD5755_DAC_DC_DC_EN BIT(4)
55 #define AD5755_DAC_VOLTAGE_OVERRANGE_EN BIT(3)
60 #define AD5755_EXT_DC_DC_COMP_RES BIT(6)
64 #define AD5755_SLEW_ENABLE BIT(12)
[all …]
/linux-6.14.4/drivers/pwm/
Dpwm-tegra.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/pwm/pwm-tegra.c
5 * Tegra pulse-width-modulation controller driver
7 * Copyright (c) 2010-2020, NVIDIA Corporation.
8 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <[email protected]>
11 * 1. 13-bit: Frequency division (SCALE)
12 * 2. 8-bit : Pulse division (DUTY)
13 * 3. 1-bit : Enable bit
18 * achieved is (max rate of source clock) / 256.
19 * e.g. if source clock rate is 408 MHz, maximum output frequency can be:
[all …]
/linux-6.14.4/drivers/clk/xilinx/
Dclk-xlnx-clock-wizard.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013 - 2021 Xilinx
14 #include <linux/clk-provider.h>
29 #define WZRD_CLKOUT0_FRAC_EN BIT(18)
41 #define WZRD_CLKFBOUT_FRAC_EN BIT(1)
42 #define WZRD_CLKFBOUT_PREDIV2 (BIT(11) | BIT(12) | BIT(9))
43 #define WZRD_MULT_PREDIV2 (BIT(10) | BIT(9) | BIT(12))
44 #define WZRD_CLKFBOUT_EDGE BIT(8)
45 #define WZRD_P5EN BIT(13)
47 #define WZRD_P5FEDGE BIT(15)
[all …]
/linux-6.14.4/drivers/i2c/busses/
Di2c-st.c1 // SPDX-License-Identifier: GPL-2.0-only
51 #define SSC_CTL_HB BIT(4)
52 #define SSC_CTL_PH BIT(5)
53 #define SSC_CTL_PO BIT(6)
54 #define SSC_CTL_SR BIT(7)
55 #define SSC_CTL_MS BIT(8)
56 #define SSC_CTL_EN BIT(9)
57 #define SSC_CTL_LPB BIT(10)
58 #define SSC_CTL_EN_TX_FIFO BIT(11)
59 #define SSC_CTL_EN_RX_FIFO BIT(12)
[all …]
/linux-6.14.4/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/
Ddm.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2014 Realtek Corporation.*/
19 struct false_alarm_statistics *falsealm_cnt = &rtlpriv->falsealm_cnt; in rtl92ee_dm_false_alarm_counter_statistics()
21 rtl_set_bbreg(hw, DM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1); in rtl92ee_dm_false_alarm_counter_statistics()
22 rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTD_11N, BIT(31), 1); in rtl92ee_dm_false_alarm_counter_statistics()
25 falsealm_cnt->cnt_fast_fsync_fail = (ret_value & 0xffff); in rtl92ee_dm_false_alarm_counter_statistics()
26 falsealm_cnt->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16); in rtl92ee_dm_false_alarm_counter_statistics()
29 falsealm_cnt->cnt_ofdm_cca = (ret_value & 0xffff); in rtl92ee_dm_false_alarm_counter_statistics()
30 falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16); in rtl92ee_dm_false_alarm_counter_statistics()
33 falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff); in rtl92ee_dm_false_alarm_counter_statistics()
[all …]
/linux-6.14.4/tools/include/uapi/linux/
Dpkt_sched.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
12 with obsolete IPv6 values is not occasional :-). New IPv6 drafts
39 __u32 bps; /* Current flow byte rate */
40 __u32 pps; /* Current flow packet rate */
51 ---------
53 All the traffic control objects have 32bit identifiers, or "handles".
96 __u32 rate; member
119 #define TCA_STAB_MAX (__TCA_STAB_MAX - 1)
130 * Priorities go from zero to (SKBPRIO_MAX_PRIORITY - 1).
149 __u8 priomap[TC_PRIO_MAX+1]; /* Map: logical priority -> PRIO band */
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/sound/
Dcs35l36.txt5 - compatible : "cirrus,cs35l36"
7 - reg : the I2C address of the device for I2C
9 - VA-supply, VP-supply : power supplies for the device,
13 - cirrus,boost-ctl-millivolt : Boost Voltage Value. Configures the boost
18 - cirrus,boost-peak-milliamp : Boost-converter peak current limit in mA.
24 - cirrus,boost-ind-nanohenry : Inductor estimation LBST reference value.
32 - cirrus,multi-amp-mode : Boolean to determine if there are more than
33 one amplifier in the system. If more than one it is best to Hi-Z the ASP
36 - cirrus,boost-ctl-select : Boost converter control source selection.
39 0x00 - Control Port Value
[all …]
/linux-6.14.4/drivers/net/wireless/intel/iwlegacy/
Dcommands.h8 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
92 /* Multi-Station support */
138 /* RF-KILL commands and notifications */
184 * when sending the response to each driver-originated command, so
188 * There is one exception: uCode sets bit 15 when it originates
196 * 0:7 tfd idx - position within TX queue
199 * 14 huge - driver sets this to indicate command is in the
201 * 15 unsolicited RX or uCode-originated notification
[all …]
/linux-6.14.4/drivers/clk/pistachio/
Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
17 #define PLL_STATUS_LOCK BIT(0)
28 #define PLL_INT_CTRL1_PD BIT(24)
29 #define PLL_INT_CTRL1_DSMPD BIT(25)
30 #define PLL_INT_CTRL1_FOUTPOSTDIVPD BIT(26)
31 #define PLL_INT_CTRL1_FOUTVCOPD BIT(27)
40 #define PLL_INT_CTRL2_BYPASS BIT(28)
43 #define PLL_FRAC_CTRL3_PD BIT(0)
44 #define PLL_FRAC_CTRL3_DACPD BIT(1)
[all …]

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